TPS3825-50DBVR Datasheet TPS3825-50DBVR, TPS3824-33DBVT, X80200V20I | P10-P12

FN8154.0

The Register Block is organized as follows:

• Status Register (SR) (1 Byte). Located at address 00h.

• Remote Shut Down Register (RSR) (1 Byte). Located at

address FFh.

The Status Register provides the user a mechanism for

checking the status of GATE_H, GATE_M and GATE_L.

These bits are volatile and are read only.

The gate status values in the Status Register can be read at

any time by performing a random read operation. Only one

byte is returned by each read operation. The master should

supply a stop condition following the output byte to be

consistent with the bus protocol.

STAT_GATEH: GATEH Status Flag (volatile)

STAT_GATEH will be set to ‘1’ when the GATE_H charge

pump is turned on. It will be reset to ‘0’ when the GATE_H

charge pump is turned off.

STAT_GATEM: GATEM Status Flag (volatile)

STAT_GATEM will be set to ‘1’ when GATE_M charge pump

is turned on. It will be reset to ‘0’ when the GATE_M charge

pump is turned off.

STAT_GATEL: GATEL Status Flag (volatile)

STAT_GATEL will be set to ‘1’ when GATE_L charge pump

is turned on. It will be reset to ‘0’ when the GATE_L charge

pump is turned off.

The status register also contains a WEL bit that controls

write operations to the Shutdown Register. Bits 7, 6, 5, and 4

should always be set to ‘0’.

WEL: Write Enable Latch (Volatile)

The WEL bit controls the access to the Remote Shutdown

the LOW (disabled) state. While the WEL bit is LOW, writes

to the RSR will be ignored (no acknowledge will be issued

after the Data Byte). The WEL bit is set by writing a “1” to the

WEL bit and zeroes to the other bits of the status register.

The X80200 provides the user with a software shutdown of

GATE_H, GATE_L and GATE_M. This over-rides the normal

output control.

A write operation with data 01h to the RSR will immediately

turn off GATE_M followed by GATE_L. The GATE_L turn off

is delayed by t

DELAY_DOWN

A write operation with data 02 to the RSR will turn off

GATE_H.

A write operation with data 03 to RSR will shutdown all

gates. GATE_H turn off at the same time as GATE_M.

GATE_L turns off after a delay of t

DELAY_DOWN

A write operation with data 00h to the RSR will remove the

software override function. Assuming all supplies are good,

the X80200 will return to the previous state by first turning on

GATE_H and GATE_L. Then, GATE_M is turned on

according to the power sequencing mode chosen.

Bits 7, 6, 5, 4, 3 and 2 of the Remote Shutdown Register

should always be set to ‘0’.

The data in the RSR can be read by performing a random

read operation to the RSR. The data in the RSR powers up

in ‘0’ state.

Bus Interface Information

Interface Conventions

The device supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the

bus as a transmitter, and the receiving device as the

receiver. The device controlling the transfer is called the

master and the device being controlled is called the slave.

The master always initiates data transfers, and provides the

clock for both transmit and receive operations. Therefore,

the devices in this family operate as slaves in all

applications.

Status Register (Volatile)

76543210

0000 STAT_

GATEH

STAT_

GATEM

STAT_

GATEL

WEL

Remote Shutdown Register (RSR) (Volatile)

RSR

DATA

GATE

SHUTDOWN SEQUENCE

01 GATE_M,

GATE_L

GATE_M turns off, then after time

DELAY_DOWN

GATE_L turns off.

02 GATE_H Immediate turn off of GATE_H

03 GATE_H,

GATE_M,

GATE_L

GATE_H and GATE_M turn off, then after

time t

DELAY_DOWN

GATE_L turns off.

00 no override X80200 returns to previous condition,

assuming all supplies are good, GATE_H

and GATE_L turn on, then GATE_M turns

on according to the chosen sequence

mode.

X80200, X80201, X80202, X80203, X80204

FN8154.0

SERIAL CLOCK AND DATA

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are reserved for

indicating start and stop conditions. (See Figure 7.)

SERIAL START CONDITION

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH. The

device continuously monitors the SDA and SCL lines for the

start condition and will not respond to any command until

this condition has been met. (See Figure 8.)

SERIAL STOP CONDITION

All communications must be terminated by a stop condition,

which is a LOW to HIGH transition of SDA when SCL is

HIGH, followed by a HIGH to LOW transition on SCL. After

going LOW, SCL can stay LOW or return to HIGH. (See

Figure 8.)

Slave Address Byte

Following a START condition, the master must output a

Slave Address Byte. This byte consists of three parts:

• The Device Type Identifier which consists of the most

significant four bits of the Slave Address. The Device Type

Identifier MUST be set to 1010 in order to select the

device.

• The next 3 bits (SA3 - SA1) are slave address bits. These

bits are compared to the status of the input pins A2–A0.

• The Least Significant Bit of the Slave Address (SA0) Byte

is the R/W bit. This bit defines the operation to be

performed on the device being addressed (as defined in

the bits SA2 - SA1). When the R/W

bit is “1”, then a READ

operation is selected. A “0” selects a WRITE operation.

Word Address

The next 8 bits following the slave byte, BA7–BA0,

determine the portion of the device accessed. If all ‘0’s, then

Status Register (SR) is selected. If all ‘1’s, then the Remote

Shutdown Register (RSR) is selected.

Serial Acknowledge

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either

master or slave, will release the bus after transmitting eight

bits. During the ninth clock cycle, the receiver will pull the

SDA line LOW to acknowledge that it received the eight bits

of data. (See Figure 9.)

The device will respond with an acknowledge after

recognition of a start condition and if the correct Device

Identifier and Select bits are contained in the Slave Address

Byte. If a write operation is selected, the device will respond

with an acknowledge after the receipt of each subsequent

eight bit word. The device will acknowledge all incoming data

and address bytes, except for the Slave Address Byte when

the Device Identifier and/or Select bits are incorrect.

Write Operation

For a write operation, the device requires the Slave Address

Byte and a Word Address Byte. This gives the master

access to the registers. After receipt of the Word Address

Byte, the device responds with an acknowledge, and awaits

the next eight bits of data. After receiving the 8 bits of the

Data Byte, the device again responds with an acknowledge.

The master then terminates the transfer by generating a stop

condition. (See Figure 11, See Figure 1 for bus timing.)

In order to perform a write operation to Remote Shutdown

SCL

SDA

DATA STABLE

DATA

CHANGE

DATA STABLE

FIGURE 7. VALID DATA CHANGES ON THE SDA BUS

SCL

SDA

START STOP

FIGURE 8. VALID START AND STOP CONDITIONS

8 91

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START ACKNOWLEDGE

FIGURE 9. ACKNOWLEDGE RESPONSE FROM RECEIVER

X80200, X80201, X80202, X80203, X80204

FN8154.0

Read Operation

A Read operation is initiated in the same manner as a write

operation with the exception that the R/W

bit of the Slave

Address Byte is set to one.

Prior to issuing the Slave Address Byte with the R/W

bit set to

one, the master must first perform a “dummy” write operation.

The master issues the start condition and the Slave Address

Byte, receives an acknowledge, then issues the Word Address

Byte. After acknowledging receipt of the Word Address Byte,

the master immediately issues another start condition and the

Slave Address Byte with the R/W

bit set to one. This is followed

by an acknowledge from the device and then by the data byte

containing the register contents. The master terminates the

read operation by responding with a no-acknowledge and then

issuing a stop condition. The ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read operation,

the master must either issue a stop condition during the

ninth cycle or hold SDA HIGH during the ninth clock cycle

and then issue a stop condition.

See Figure 12 for the address, acknowledge, and data

transfer sequence. See Figure 1 for bus timing.

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• The WEL bit is set to ‘0’. It is not possible to write to the

device.

• The WEL bit must be set to allow write operations.

• SDA pin is the input mode.

• The data in the RSR powers up in ‘0’ state.

SA6SA7

SA5

SA2

SA1

SA0

DEVICE TYPE

IDENTIFIER

READ/

SA4

R/W101

WRITE

ADDRESS

INTERNAL

DEVICE

A2 A1 A0

BIT SA0 OPERATION

0WRITE

1 READ

BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0

0000000

1111111

DATA BYTE

D6 D5 D4 D3 D2 D1 D0

SLAVE ADDRESS

RSR

SA3

WORD ADDRESS

FIGURE 10. ADDRESS FORMAT

X80200, X80201, X80202, X80203, X80204

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

TPS3825-50DBVR

Mfr. #:

Buy TPS3825-50DBVR

Manufacturer:

Texas Instruments

Description:

Supervisory Circuits Processor Sprvisry Circuits

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TPS3825-50DBVR

TPS3825-50DBVR

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