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TPS3825-50DBVR
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P16
13
FN8154.0
Application Section
S
T
A
R
T
S
T
O
P
DA
T
A
A
C
K
A
C
K
SDA BUS
SIGNALS FROM
THE SLA
VE
SIGNALS FROM
THE MASTER
0
A
C
K
WORD
ADDRESS
1
0
1
0
SLA
VE
ADDRESS
DEVIC
E
ID
A0
A1
A2
FIGURE 1
1.
BYTE WRITE SEQUENCE
A
C
K
S
T
A
R
T
S
T
O
P
DA
T
A
S
T
A
R
T
SDA BUS
SIGNALS FRO
M
THE SLA
VE
SIGNALS FROM
THE MASTER
WORD
ADDRESS
A
C
K
SLA
VE
ADDRESS
0
1
0
1
0
DEVICE
ID
A
C
K
SLA
VE
ADDRESS
1
1
0
1
0
DEVICE
ID
A0
A1
A2
A0
A1
A2
A
C
K
S
T
A
R
T
S
T
O
P
DA
T
A
S
T
A
R
T
SDA BUS
SIGNALS FRO
M
THE SLA
VE
SIGNALS FROM
THE MASTER
WORD
ADDRESS
A
C
K
SLA
VE
ADDRESS
0
1
0
1
0
DEVICE
ID
A
C
K
SLA
VE
ADDRESS
1
1
0
1
0
DEVICE
ID
A0
A1
A2
A0
A1
A2
FIGURE 12.
READ SEQUENCE
DC-DC
#1
DC-DC
#2
DC-DC
#3
HOT SW
AP
CONTROLLER
-48V BACKPLANE/COMMUNICA
TION BACKPLANE
OPTIONAL
SMBus
SMBus
H (OPTIONAL)
PRIMAR
Y
I/O VOL
T
AGES
CORE VOL
T
AGES
SLA
VE
ADDRESS
PULL UP
TO S
ET
ADDRESS HIGH
SYSTEM
COMPONENTS &
BOARD SUPPLIES
I/O SUPPL
Y
CORE SUPPL
Y
µP/
ASICs/
FPGA
VCORE
V I/O
Primary
3.3V
5V
5V
2.7V
2.5V
2.0V
1.8V
1.25V
0.9V
3.3V
2.5V
1.35V
1.25V
L
M
RC DELA
Y
X80200
VDDH
VDDM
SETV
VDDL
GA
TEH_EN
SDA
SCL
GND
A2
A0
ENS
GA
TE_L
GA
TE_M
GA
TE_H
VFB
REF
READY
FIGURE 13.
TELECOM BACKPLACE/SYST
EM POWE
R SUPPL
Y VOL
T
AGE BASED POWER SEQUENCING
X80200, X80201, X80202,
X80203, X80204
14
FN8154.0
DC-DC
#1
DC-DC
#2
DC-DC
#3
HOT SW
A
P
CONTROLLER
-48V BACKPLANE/COMMUNICA
TION BACKPLANE
OPTIONAL
SMBus
SMBus
H (OPTIONAL)
PRIMARY
I/O VOL
T
AGES
CORE VOL
T
AGES
SLA
V
E
ADDRESS
PULL UP
TO SE
T
ADDRESS HIGH
OPTION
FORCED
SEQUENCING
SYSTEM
COMPONENTS &
BOARD SUPPLIES
I/O SUPPL
Y
CORE SUPPL
Y
µP/
ASICs/
FPGA
VCORE
V I/O
Primary
3.3V
5V
5V
2.7V
2.5V
2.0V
1.8V
1.25V
0.9V
3.3V
2.5V
1.35V
1.25V
VCORE
L
M
PGOOD1
PGOOD2
DELA
Y
VDDH
VDDM
SETV
VDDL
GA
TEH_EN
SDA
SCL
GND
A2
A0
ENS
GA
TE_L
GA
TE_
M
GA
TE_H
VFB
REF
READY
FIGURE 14.
TELECOM BACKPLACE/SYSTEM POWER SUPPL
Y TIME BASED POWER SEQUENCING
X80200, X80201, X80202,
X80203, X80204
15
FN8154.0
DC-DC
#1
OPTION
SMBus
SMBus
H (OPTIONAL)
PRIMAR
Y
V I/O
V
ID4:ID0
SLA
VE
ADDRESS
PULL UP
TO SET
ADDRESS HIGH
OPTIONAL
FORCED
SEQUENCING
SYSTEM
COMPONENTS &
BOARD SUPPLIES
VCORE
V I/O
Primary
3.3V
5V
5V
2.7V
2.5V
2.0V
1.8V
1.25V
0.9V
3.3V
2.5V
1.35V
1.25V
DC-DC
#2
V
ID4:IDO
VCORE
PWRGD
SCL
SDA
VRM
POWER
SUPPL
Y
I/O SUPPL
Y
CORE SUPPL
Y
µP/
ASICs/
FPGA
M
POWER SEQUENCING (TIME BASED MODE)
USING POWER GOOD SIGNALS
DELA
Y
10
7,8,55-
57
5
9
OUTEN
PGOOD1
53
NC
X80200
VDDH
VDDM
SETV
VDDL
GA
TEH_
EN
SDA
SCL
GND
A2
A0
ENS
GA
TE_
L
GA
TE_M
GA
TE_
H
VFB
REF
READY
FIGURE 15.
POWER SEQUENCING OF VRM SUPPLIES
X80200, X80201, X80202,
X80203, X80204
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P16
TPS3825-50DBVR
Mfr. #:
Buy TPS3825-50DBVR
Manufacturer:
Texas Instruments
Description:
Supervisory Circuits Processor Sprvisry Circuits
Lifecycle:
New from this manufacturer.
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