OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

83940DY-01LF

P1-P3P4-P6P7-P9P10-P12P13-P15
Low Skew, 1-to-18
LVPECL-TO-LVCMOS / LVTTL Fanout Buffer
83940-01
DATASHEET
83940-01 REVISION A NOVEMBER 4, 2014 1 ©2014 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The ICS83940-01 is a low skew, 1-to-18 LVPECL-to-LVCMOS/LVTTL
Fanout Buffer. The ICS83940-01 has two selectable clock inputs. The
PCLK, nPCLK pair can accept LVPECL, CML or SSTL input levels. The
single ended clock input accepts LVCMOS or LVTTL input levels. The low
impedance LVCMOS/LVTTL outputs are designed
to drive 50Ω series or parallel terminated transmis-
sion lines. The effective fanout can be increased from 18 to
36 by utilizing the ability of the outputs to drive two series
terminated lines.
The ICS83940-01 is characterized at full 3.3V, full 2.5V
and mixed 3.3V input and 2.5V output operat-
ing supply modes. Guaranteed output and part-to-part skew
characteristics make the ICS83940-01 ideal for those clock
distribution applications demanding well defined
performance and repeatability.
BLOCK DIAGRAM PIN ASSIGNMENT
32-Lead LQFP
Y Pacakge
7mm x 7mm x 1.4mm package body
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q6
Q7
Q8
V
DDO
Q9
Q10
Q11
GND
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
VDDO
VDDO
Q12
Q13
Q14
GND
Q15
Q16
Q17
GND
Q5
Q4
Q3
V
DDO
Q2
Q1
Q0
ICS83940-01
FEATURES
• Eighteen LVCMOS/LVTTL outputs, 23Ω typical output impedance
• Selectable LVCMOS_CLK or LVPECL clock inputs
• LVCMOS_CLK supports the following input types:
LVCMOS or LVTTL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 250MHz
• Output skew: 85ps (maximum)
• Part-to-part skew: 750ps (maximum)
• Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Available in lead-free RoHS compliant package
Q0:Q17
CLK_SEL
PCLK
nPCLK
LVCMOS_CLK
0
1
18
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
83940-01 DATA SHEET
2 REVISION A 11/4/14
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
TABLE 3A. CLOCK SELECT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Control Input Clock
CLK_SEL PCLK, nPCLK LVCMOS_CLK
0 Selected De-selected
1 De-selected Selected
Inputs Outputs
Input to Output Mode Polarity
CLK_SEL LVCMOS_CLK PCLK nPCLK Q0:Q17
0 — 0 1 LOW Differential to Single Ended Non Inverting
0 — 1 0 HIGH Differential to Single Ended Non Inverting
0— 0
Biased;
NOTE 1
LOW Single Ended to Single Ended Non Inverting
0— 1
Biased;
NOTE 1
HIGH Single Ended to Single Ended Non Inverting
0 — Biased; NOTE 1 0 HIGH Single Ended to Single Ended Inverting
0 — Biased; NOTE 1 1 LOW Single Ended to Single Ended Inverting
1 0 — — LOW Single Ended to Single Ended Non Inverting
1 1 — — HIGH Single Ended to Single Ended Non Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
Number Name Type Description
1, 2, 12, 17, 25 GND Power Power supply ground.
3 LVCMOS_CLK Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
4 CLK_SEL Input Pulldown
Clock select input. Selects LVCMOS / LVTTL clock
input when HIGH. Selects PCLK, nPCLK inputs when
LOW. LVCMOS / LVTTL interface levels.
5 PCLK Input Pulldown Non-inverting differential LVPECL clock input.
6 nPCLK Input
Inverting differential LVPECL clock input.
V
DD
/2 default when left fl oating.
7V
DD
Power Power supply pin.
8, 16, 21, 29 V
DDO
Power Output supply pins.
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
Q17, Q16, Q15, Q14, Q13,
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Output Clock outputs. LVCMOS / LVTTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
C
PD
Power Dissipation Capacitance
(per output)
6pF
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
R
OUT
Output Impedance 18 28
Ω
REVISION A 11/4/14
83940-01 DATA SHEET
3 LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
3.6V
Inputs, V
I
-0.3V to V
DD
+ 0.3V
Outputs, V
O
-0.3V to V
DDO
+ 0.3V
Input Current, I
IN
±20mA
Storage Temperature, T
STG
-40°C to 125°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V ± 5%, TA = 0° TO 70°
TABLE 4B. DC CHARACTERISTICS, V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, TA = 0° TO 70°
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage LVCMOS_CLK 2.4 V
DD
V
V
IL
Input Low Voltage LVCMOS_CLK 0.8 V
V
PP
Peak-to-Peak Input Voltage PCLK, nPCLK 500 1000 mV
V
CMR
Input Common Mode Voltage;
NOTE 1, 2
PCLK, nPCLK V
DD
- 1.4 V
DD
- 0.6 V
I
IN
Input Current ±200 µA
V
OH
Output High Voltage I
OH
= -20mA 2.4 V
V
OL
Output Low Voltage I
OL
= 20mA 0.5 V
I
DD
Power Supply Current 25 mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is
V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defi ned as
V
IH
.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage LVCMOS_CLK 2.4 V
DD
V
V
IL
Input Low Voltage LVCMOS_CLK 0.8 V
V
PP
Peak-to-Peak Input Voltage PCLK, nPCLK 300 1000 mV
V
CMR
Input Common Mode Voltage;
NOTE 1, 2
PCLK, nPCLK V
DD
- 1.4 V
DD
- 0.6 V
I
IN
Input Current ±200 µA
V
OH
Output High Voltage I
OH
= -20mA 1.8 V
V
OL
Output Low Voltage I
OL
= 20mA 0.5 V
I
DD
Power Supply Current 25 mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is
V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defi ned as
V
IH
.
P1-P3P4-P6P7-P9P10-P12P13-P15

83940DY-01LF

Mfr. #:
Buy 83940DY-01LF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 18 LVCMOS OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet