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83940DY-01LF

P1-P3P4-P6P7-P9P10-P12P13-P15
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
83940-01 DATA SHEET
10 REVISION A 11/4/14
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and oth-
er differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 2A to 2E show
interface examples for the PCLK/nPCLK input driven
by the most common driver types. The input interfaces
suggested here are examples only. If the driver is from
another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confi rm the
driver termination requirements.
FIGURE 2A. PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 2B. PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
FIGURE 2C. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2F. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
FIGURE 2E. PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PCL K /nPCL K
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
FIGURE 2D. PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
REVISION A 11/4/14
83940-01 DATA SHEET
11 LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS83940-01 is: 819
TABLE 6. θ
JA
VS. AIR FLOW TABLE FOR 32 LEAD LQFP
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
83940-01 DATA SHEET
12 REVISION A 11/4/14
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
BBA
MINIMUM NOMINAL MAXIMUM
N
32
A
-- -- 1.60
A1
0.05 -- 0.15
A2
1.35 1.40 1.45
b
0.30 0.37 0.45
c
0.09 -- 0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45 0.60 0.75
θ
0° -- 7°
ccc
-- -- 0.10
Reference Document: JEDEC Publication 95, MS-026
P1-P3P4-P6P7-P9P10-P12P13-P15

83940DY-01LF

Mfr. #:
Buy 83940DY-01LF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 18 LVCMOS OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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