LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
83940-01 DATA SHEET
4 REVISION A 11/4/14
TABLE 5A. AC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V ± 5%, TA = 0° TO 70°
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
t
pLH
Propagation Delay
PCLK, nPCLK;
NOTE 1, 5
f 150MHz
1.6 3.0 ns
LVCMOS_CLK;
NOTE 2, 5
f 150MHz
1.8 3.0 ns
t
pLH
Propagation Delay
PCLK, nPCLK;
NOTE 1, 5
f > 150MHz
1.6 3.3 ns
LVCMOS_CLK;
NOTE 2, 5
f > 150MHz 1.8 3.2 ns
tsk(o)
Output Skew;
NOTE 3, 5
PCLK, nPCLK
Measured on
rising edge @V
DDO
/2
85 ps
LVCMOS_CLK 85 ps
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
f 150MHz
1.4 ns
LVCMOS_CLK
f 150MHz
1.2 ns
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
f > 150MHz
1.7 ns
LVCMOS_CLK
f > 150MHz
1.4 ns
tsk(pp)
Part-to-Part Skew;
NOTE 4, 5
PCLK, nPCLK
Measured on
rising edge @V
DDO
/2
850 ps
LVCMOS_CLK 750 ps
t
R
, t
F
Output Rise/Fall Time 20% to 80% 400 800 ps
odc Output Duty Cycle
f 150MHz
45 55 %
150MHz < f 250MHz
40 60 %
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output V
DDO
/2.
NOTE 2: Measured from V
DD
/2 to V
DDO
/2.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 6: Defi ned as skew between outputs on different devices, across temperature and voltage ranges, and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
TABLE 4C. DC CHARACTERISTICS, V
DD
= V
DDO
= 2.5V±5%, TA = 0° TO 70°
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage LVCMOS_CLK 2 V
DD
V
V
IL
Input Low Voltage LVCMOS_CLK 0.8 V
V
PP
Peak-to-Peak
Input Voltage
PCLK, nPCLK 300 1000 mV
V
CMR
Input Common Mode Voltage;
NOTE 1, 2
PCLK, nPCLK V
DD
- 1.4 V
DD
- 0.6 V
I
IN
Input Current ±200 µA
V
OH
Output High Voltage I
OH
= -12mA 1.8 V
V
OL
Output Low Voltage I
OL
= 12mA 0.5 V
I
DD
Power Supply Current 25 mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is
V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defi ned as
V
IH
.
