NOTES
1
ENABLE pin is grounded. IN0 = +1 V dc, IN1 = –1 V dc. SELECT input is driven with 0 V to +5 V pulse. Measure transition time from 50% of the SELECT input value
(+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (–1 V), or vice versa.
2
ENABLE pin is driven with 0 V to +5 V pulse (with 3 ns edges). State of SELECT input determines which channel is activated (i.e., if SELECT = Logic 0, IN0 is selected). Set
IN0 = +1 V dc, IN1 = –1 V dc, and measure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5, ∆t
OFF
is the disable
time,
∆t
ON
is the enable time.
3
All inputs are grounded. SELECT input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT pulse increases the glitch magnitude
due to coupling via the ground plane. Removing the SELECT input termination will lower glitch, as does increasing R
L
.
4
Decreasing R
L
lowers the bandwidth slightly. Increasing C
L
lowers the bandwidth considerably (see Figure 19).
5
A resistor (R
S
) placed in series with the mux inputs serves to optimize 0.1 dB flatness, but is not required. Increasing output capacitance will increase peaking and reduce band-
width (see Figure 20.)
6
Select input which is not being driven (i.e., if SELECT is Logic 1, input activated is IN1); drive all other inputs with V
IN
= 0.707 V rms and monitor output at ƒ = 5 and 30 MHz.
R
L
= 1 kΩ (see Figure 13).
7
Mux is disabled (i.e., ENABLE = Logic 1) and all inputs are driven simultaneously with V
IN
= 0.446 V rms. Output is monitored at ƒ = 5 and 30 MHz. R
L
= 30 Ω to simulate
R
ON
of one enabled mux within a system (see Figure 14). In this mode the output impedance is very high (typ 10 MΩ), and the signal couples across the package; the load imped-
ance determines the crosstalk.
8
Voltage gain decreases for lower values of R
L
. The resistive divider formed by the mux enabled output resistance (27 Ω) and R
L
causes a gain which decreases as R
L
decreases
(i.e., the voltage gain is approximately 0.97 V/V (3% gain error) for R
L
= 1 kΩ).
9
Larger values of R
L
provide wider output voltage swings, as well as better gain accuracy. See Note 8.
Specifications subject to change without notice.
AD8180/AD8182
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8180/AD8182 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–3–
REV. B
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Internal Power Dissipation
2
AD8180 8-Lead Plastic DIP (N) . . . . . . . . . . . . . . . . 1.3 Watts
AD8180 8-Lead Small Outline (R) . . . . . . . . . . . . . . 0.9 Watts
AD8182 14-Lead Plastic DIP (N) . . . . . . . . . . . . . . . 1.6 Watts
AD8182 14-Lead Small Outline (R) . . . . . . . . . . . . . 1.0 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
S
Output Short Circuit Duration . . . . . Observe Power Derating Curves
Storage Temperature Range
N and R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . +300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air: 8-Lead Plastic DIP Package: θ
JA
= 90°C/W;
8-Lead SOIC Package: θ
JA
= 155°C/W; 14-Lead Plastic Package: θ
JA
= 75°C/W;
14-Lead SOIC Package: θ
JA
= 120°C/W, where P
D
= (T
J
–T
A
)/θ
JA
.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD8180AN –40°C to +85°C 8-Lead Plastic DIP N-8
AD8180AR –40°C to +85°C 8-Lead SOIC SO-8
AD8180AR-REEL –40°C to +85°C 13" Reel SOIC SO-8
AD8180AR-REEL7 –40°C to +85°C 7" Reel SOIC SO-8
AD8182AN –40°C to +85°C 14-Lead Plastic DIP N-14
AD8182AR –40°C to +85°C 14-Lead Narrow SOIC R-14
AD8182AR-REEL –40°C to +85°C 13" Reel SOIC R-14
AD8182AR-REEL7 –40°C to +85°C 7" Reel SOIC R-14
AD8180-EB Evaluation Board
AD8182-EB Evaluation Board
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8180 and AD8182 is limited by the associated rise in junc-
tion temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150°C. Exceeding
this limit temporarily may cause a shift in parametric perfor-
mance due to a change in the stresses exerted on the die by the
package. Exceeding a junction temperature of +175°C for an
extended period can result in device failure.
While the AD8180 and AD8182 are internally short circuit
protected, this may not be sufficient to guarantee that the maxi-
mum junction temperature (+150°C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe
the maximum power derating curves shown in Figures 2 and 3.
MAXIMUM POWER DISSIPATION – Watts
AMBIENT TEMPERATURE – 8C
2.0
1.5
0
–50 90–40 –30 –20 –10 0 10 20 30 50 60 70 8040
1.0
0.5
8-LEAD PLASTIC DIP PACKAGE
8-LEAD SOIC PACKAGE
T
J
= +1508C
Figure 2. AD8180 Maximum Power Dissipation vs.
Temperature
AMBIENT TEMPERATURE – 8C
2.5
2.0
0.5
–50 90–40
MAXIMUM POWER DISSIPATION – Watts
–30 –20 –10 0 10 20 30 40 50 60 80
1.5
1.0
70
14-LEAD SOIC
14-LEAD
PLASTIC DIP PACKAGE
T
J
= +1508C
Figure 3. AD8182 Maximum Power Dissipation vs.
Temperature
WARNING!
ESD SENSITIVE DEVICE
