MP86885 – INTELLI-PHASE SOLUTION IN 4x6mm TQFN
MP86885 Rev. 1.01 www.MonolithicPower.com 12
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PCB Layout Guide Line
PCB layout plays an important role to achieve
stable operation. For optimal performance, follow
these guidelines. The sample layout at the end of
these guidelines can be used as a layout
reference.
1. Always place some input bypass ceramic
capacitors next to the device and on the
same layer as the device. Do not put all of
the input bypass capacitors on the back side
of the device. Use as many via and input
voltage planes as possible to reduce
switching spikes. Place the BST capacitor
and the VDRV capacitor as close to the
device as possible.
2. Place the VDD decoupling capacitor close to
the device. Connect AGND and PGND at the
point of VDD capacitor's ground connection.
3. It is recommended to use 0.22µF to 1µF
bootstrap capacitor and 3.3Ω bootstrap
resistance. Do not use capacitance values
below 100nF for the BST capacitor.
4. Connect IN, SW and PGND to large copper
areas and use via to cool the chip to improve
thermal performance and long-term reliability.
5. Keep the path of switching current short and
minimize the loop area formed by the input
capacitor. Keep the connection between the
SW pin and the input power ground as short
and wide as possible.
Figure 5: Sample PCB Layout
