3
ICS1574B
PCLK Programmable Divider
The ICS1574B has a programmable divider (referred to in Fig-
ure 1 as the PCLK divider) that is used to generate the PCLK
clock frequency for the pixel clock output. The modulus of
this divider may be set to 3, 4, 5, 6, 8, 10, 12, 16 or 20 under
register control. The design of this divider permits the output
duty factor to be 50/50, even when an odd modulus is se-
lected. The input frequency to this divider is the output of the
PLL post-scaler described below:
The phase of the PCLK output is aligned with the internal
high frequency PLL clock (F
VCO
) immediately after the asser-
tion of the PCLKEN input pulse (active low if PCLKEN_POL
bit is 0 or active high if PCLKEN_POL bit is 1).
When PCLKEN is deasserted, the PCLK output will complete
its current cycle and remain at VDD until the next PCLKEN
pulse. The minimum time PCLKEN must be disabled
(T
PULSE
) is 1/F
PCLK
.
See Figure 2a for an example of PCLKEN enable (negative
polarity) vs. PCLK timing sequences.
Figure 2a
Figure 2b
seulaVK
rediviDKLCPK
32
a45.3
b43
55.4
65.3
a85.5
b85
017
215.6
a615.9
b619
0221
T
K
= K •T
VCO
T
d
= LOGIC PROP.DELAY TIME
(typically 9ns with a 10pF load on PCLK)
T
VCO
= 1/F
VCO
The resolution of Ton is one VCO cycle.
The time required for a PCLK cycle start following a PCLKEN
enable is described by Figure 2b and the following table:
Typical values for Tr and Tf with a 10pF load on PCLK are
1ns.
