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ICS1574BM

P1-P3P4-P6P7-P9P10-P12
7
ICS1574B
]3[KLCP]2[KLCP]1[KLCP]0[KLCPSULUDOM
0000 3
0001 )a(4
0010 )b(4
0011 5
0100 6
0101 )a(8
0110 )b(8
0111 01
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1X 1 0 )b(61
1X 1 1 02
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Register Mapping — ICS1574B
NOTE: It is not necessary to understand the function of these bits to use the ICS1574B. PC Software is available from ICS to
automatically generate all register values based on requirements. Contact factory for details.
BIT(S) BIT REF. DESCRIPTION
1 – 4 PCLK[0]..PCLK[3] Sets PCLK divider modulus according to this table.
These bits are set to implement a divide-by-four on power-up.
(X = Don't Care)
5, 6 Reserved Must be set to 0.
7 Reserved Must be set to 1.
8 SELXTAL Normally set to 0. When set to logic 1, passes the reference
frequency to the post-scaler instead of the PLL output
(defaults to 1 on power-up).
9 Reserved Must be set to 0.
10 Reserved Must be set to 1.
11, 12 Reserved Must be set to 0.
13 – 14 S[0]..S[1] PLL post-scaler / test mode select bits.
ICS1574B
8
]1[P]0[PNIAG
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00 50.0
01 51.0
10 5.0
11 5.1
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100 03
10 1 54
110 06
111 08
BIT
(
S
)
BIT REF
.
DESCRIPTION
15 Reserved Must be set to 0.
16 AUX_PCLK Must be set to 0 except when in the AUX-EN test mode.
When in the AUX-EN test mode, this bit controls the
PCLK output.
17 – 24 Reserved Must be set to 0.
25 – 27 V[0]..V[2] Sets the gain of VCO
28 Reserved Must be set to 1.
29 – 30 P[0]..P[1] Sets the gain of the phase detector according to this table:
31 Reserved Must be set to 0.
32 P[2] Phase detector tuning bit. Should normally be set to one.
See text.
33 – 38 M[0]..M[5] M counter control bits. Modulus = value + 1.
39 PCLKEN_POL When = 0, PCLK output enabled when PCLKEN input is
low. When = 1, PCLK output enabled when PCLKEN input
is high.
40 DBLFREQ Doubles modulus of dual-modulus prescaler (from 6 /7 to
12/14).
41 – 44 A[0]..A[3] Controls A counter. When set to zero, modulus = 7.
Otherwise, modulus = 7 for "value" underflows of the
prescaler, and modulus = 6 thereafter until M counter
underflows.
9
ICS1574B
BIT(S) BIT REF. DESCRIPTION
45 Reserved Must be set to 1.
46 PCLK_EN Must be set to 0.
Disables the PCLK divider when set to 1 regardless of
PCLKEN input state.
47, 48 Reserved Must be set to 0.
49 – 55 R[0]..R[6] Reference divider modulus control bits.
Modulus = value +1.
56 REF_POL PLL locks to rising edge of XTAL1 input when
REFPOL = 1, falling edge of XTAL1 when REFPOL = 0.
P1-P3P4-P6P7-P9P10-P12

ICS1574BM

Mfr. #:
Buy ICS1574BM
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Description:
IC CLOCK GEN PROGR LASER 16-SOIC
Lifecycle:
New from this manufacturer.
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