ICS1574BM Datasheet 1574BMLFT, 1574BMLF, ICS1574BM | P4-P6

ICS1574B

PLL Post-Scaler

A programmable post-scaler may be inserted between the

VCO and the PCLK divider of the ICS1574B. This is useful in

generating lower frequencies, as the VCO has been optimized

for high-frequency operation. The post-scaler is not affected

by the PCLKEN input.

The post-scaler allows the selection of:

• VCO frequency

• VCO frequency divided by 2

• VCO frequency divided by 4

• AUX-EN Test Mode

PLL Synthesizer Description —

Ratiometric Mode

The ICS1574B generates its output frequencies using phase-

locked loop techniques. The phase-locked loop (or PLL) is a

closed-loop feedback system that drives the output frequency

to be ratiometrically related to the reference frequency pro-

vided to the PLL (see Figure 1). The reference frequency is

generated by an on-chip crystal oscillator or the reference fre-

quency may be applied to the ICS1574B from an external

frequency source.

The phase-frequency detector shown in the block diagram

drives the voltage-controlled oscillator, or VCO, to a fre-

quency that will cause the two inputs to the phase-frequency

detector to be matched in frequency and phase. This occurs

when:

back divider makes use of a dual-modulus prescaler tech-

nique that allows the programmable counters to operate at

low speed without sacrificing resolution. This is an improve-

ment over conventional fixed prescaler architectures that

typically impose a factor-of-four (or larger) penalty in this re-

spect.

Table 1 permits the derivation of “A” & “M” converter pro-

gramming directly from desired modulus.

Digital Inputs

The programming of the ICS1574B is performed serially

by using the DATCLK, DATA, and HOLD pins to load an

internal shift register.

DATA is shifted into the register on the rising edge of

DATCLK. The logic value on the HOLD pin is latched at

the same time. When HOLD is low, the shift register may

be loaded without disturbing the operation of the

ICS1574B. When high, the shift register outputs are trans-

ferred to the control registers, and the new programming

information becomes active. Ordinarily, a high level

should be placed on the HOLD pin when the last data bit is

presented. See Figure 3 for the programming sequence.

The PCLKEN input polarity may be programmed under

(VCO)

: =

F(XTAL1)

• Feedback Divider

Reference Divider

Figure 3

This expression is exact; that is, the accuracy of the output

frequency depends solely on the reference frequency pro-

vided to the part (assuming correctly programmed dividers).

The VCO gain is programmable, permitting the ICS1574B to

be optimized for best performance at all operating frequen-

cies.

The reference divider may be programmed for any modulus

from 1 to 128 in steps of one.

The feedback divider may be programmed for any modulus

from 37 through 392 in steps of one. Any even modulus from

392 through 784 can also be achieved by setting the “double”

bit which doubles the feedback divider modulus. The feed-

Output Description

The PCLK output is a high-current CMOS type drive

whose frequency is controlled by a programmable divider

that may be selected for a modulus of 3, 4, 5, 6, 8, 10, 12,

16 or 20. It may also be suppressed under register control

via Bit 46.

ICS1574B

NIAGOCVYCNEUQERFXAM

4zHM001

5zHM002

6zHM003

7zHM004

Reference Oscillator

and Crystal Selection

The ICS1574B has circuitry on-board to implement a

Pierce oscillator with the addition of only one external

component, a quartz crystal. Pierce oscillators operate the

crystal in

anti- (also called parallel-) resonant mode. See the AC

Characteristics for the effective capacitive loading to

specify when ordering crystals.

Series-resonant crystals may also be used with the

ICS1574B. Be aware that the oscillation frequency will be

slightly higher than the frequency that is stamped on the

can (typically 0.025 – 0.05%).

As the entire operation of the phase-locked loop depends

on having a stable reference frequency, we recommend

that the crystal be mounted as closely as possible to the

package. Avoid routing digital signals or the ICS1574B

outputs underneath or near these traces. It is also desirable

to ground the crystal can to the ground plane, if possible.

If an external reference frequency source is to be used with

the ICS1574B, it is important that it be jitter-free. The ris-

ing and falling edges of that signal should be fast and free

of noise for best results.

The loop phase can be locked to either the rising or falling

edges of the XTAL1 input signals, and is controlled by

Bit 56.

Power-On Initialization

The ICS1574B has an internal power-on reset circuit that

performs the following functions:

1) Selects the modulus of the PCLK divider to

be four (4).

2) Sets the multiplexer to pass the reference

frequency to PCLK divider input.

These functions should allow initialization for most appli-

cations that cannot immediately provide for register

programming upon system power-up.

Because the power-on reset circuit is on the VDD supply,

and because that supply is filtered, care must be taken to

allow the reset to de-assert before programming. A safe

guideline is to allow 20 microseconds after the VDD sup-

ply reaches 4 volts.

Programming Notes

• VCO Frequency Range: Use the post-divider to keep the

VCO frequency as high as possible within its operating

range.

• Divider Range: For best results in normal situations

keep the reference divider modulus as short as possible

(for a frequency at the output of the reference divider in

the few hundred kHz to several MHz range). If you

need to go to a lower phase comparator reference fre-

quency (usually required for increased frequency

accuracy), that is acceptable, but jitter performance will

suffer somewhat.

• VCO Gain Programming: Use the minimum gain which

can reliably achieve the VCO frequency desired, as

shown here:

• Phase Detector Gain: For most applications and divider

ranges, set P [1, 0] = 10 and set P[2] = 1. Under some

circumstances, setting the P [2] bit “on” can reduce

jitter. During operation at exact multiples of the crystal

frequency, P[2] bit = 0 may provide the best jitter per-

formance.

Board Test Support

It is often desirable to statically control the levels of the

output pins for circuit board test. The ICS1574B supports

this through a register programmable mode, AUX-EN.

When this mode is set, a register bit directly controls the

logic level of the PCLK pin. This mode is activated when

the S[0] and S[1] bits are both set to logic 1. See Register

Mapping for details.

ICS1574B

Figure 4

Power Supplies and Decoupling

The ICS1574B has two VSS pins to reduce the effects of

package inductance. Both pins are connected to the same

potential on the die (the ground bus). BOTH of these pins

should connect to the ground plane of the PCB as close to

the package as is possible.

The ICS1574B has a VDDO pin which is the supply of +5

volt power to the output driver. This pin should be con-

nected to the power plane (or bus) using standard

high-frequency decoupling practice. That is, capacitors

should have low series inductance and be mounted close to

the ICS1574B.

The VDD pin is the power supply pin for the PLL synthe-

sizer circuitry and other lower current digital functions.

We recommend that RC decoupling or zener regulation be

provided for this pin (as shown in the recommended appli-

cation circuitry). This will allow the PLL to “track”

through power supply fluctuations without visible effects.

See Figure 4 for typical external circuitry.

P1-P3 P4-P6 P7-P9 P10-P12

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