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LTC3727LXEUH-1#PBF

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LTC3727LX-1
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circuit ripple current is determined by the minimum on-
time t
ON(MIN)
of the LTC3727LX-1 (less than 200ns), the
input voltage and inductor value:
∆I
L(SC)
= t
ON(MIN)
(V
IN
/L)
The resulting short-circuit current is:
I
mV
R
I
SC
SENSE
LSC
=+
45 1
2
∆
()
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.
A comparator monitors the output for overvoltage condi-
tions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
off and the bottom MOSFET is turned on until the overvolt-
age condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if V
OUT
returns to a safe level,
normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
open the system fuse. The switching regulator will regu-
late properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.
Phase-Locked Loop and Frequency Synchronization
The LTC3727LX-1 has a phase-locked loop comprised of
an internal voltage controlled oscillator and phase detec-
tor. This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the
center frequency f
O
. A voltage applied to the PLLFLTR pin
of 1.2V corresponds to a frequency of approximately
380kHz. The nominal operating frequency range of the
LTC3727LX-1 is 250kHz to 550kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆f
H
, is equal to the capture range, ∆f
C:
∆f
H
= ∆f
C
= ±0.5 f
O
(250kHz-550kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin.
If the external frequency (f
PLLIN
) is greater than the oscil-
lator frequency f
0SC
, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f
0SC
, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal fre-
quencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time correspond-
ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor C
LP
holds the voltage. The
LTC3727LX-1 PLLIN pin must be driven from a low
impedance source such as a logic gate located close to the
pin. When using multiple LTC3727LX-1s for a phase-
locked system, the PLLFLTR pin of the master oscillator
should be biased at a voltage that will guarantee the slave
oscillator(s) ability to lock onto the master’s frequency. A
DC voltage of 0.7V to 1.7V applied to the master oscillator’s
PLLFLTR pin is recommended in order to meet this
requirement. The resultant operating frequency can range
from 310kHz to 470kHz.
The loop filter components (C
LP
, R
LP
) smooth out the current
pulses from the phase detector and provide a stable input
to the voltage controlled oscillator. The filter components
C
LP
and R
LP
determine how fast the loop acquires lock.
Typically R
LP
=10kΩ and C
LP
is 0.01µF to 0.1µF.
Minimum On-Time Considerations
Minimum on-time t
ON(MIN)
is the smallest time duration
that the LTC3727LX-1 is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
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LTC3727LX-1
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cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
t
V
Vf
ON MIN
OUT
IN
()
()
<
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3727LX-1 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3727LX-1 is generally
less than 200ns. However, as the peak sense voltage
decreases the minimum on-time gradually increases up to
about 300ns. This is of particular concern in forced
continuous applications with low ripple current at light
loads. If the duty cycle drops below the minimum on-time
limit in this situation, a significant amount of cycle skip-
ping can occur with correspondingly larger inductor cur-
rent and output voltage ripple.
FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced on
both controllers when the FCB pin drops below 0.8V.
During continuous mode, current flows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
When primary load currents are low and/or the V
IN
/V
OUT
ratio is low, the synchronous switch may not be on for a
sufficient amount of time to transfer power from the
output capacitor to the secondary load. Forced continuous
operation will support secondary windings providing there
is sufficient synchronous switch duty factor. Thus, the
FCB input pin removes the requirement that power must
be drawn from the inductor primary in order to extract
power from the auxiliary windings. With the loop in
continuous mode, the auxiliary outputs may nominally be
loaded without regard to the primary output load.
The secondary output voltage V
SEC
is normally set as
shown in Figure 6 by the turns ratio N of the transformer:
V
SEC
≅ (N + 1) V
OUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V
SEC
will droop. An external resistive divider from
V
SEC
to the FCB pin sets a minimum voltage V
SEC(MIN)
:
VV
R
R
SEC MIN()
.≅ +
⎛
⎝
⎜
⎞
⎠
⎟
08 1
6
5
where R5 and R6 are shown in Figure 2.
If V
SEC
drops below this level, the FCB voltage forces
temporary continuous switching operation until V
SEC
is
again above its minimum.
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.18µA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
The following table summarizes the possible states avail-
able on the FCB pin:
Table 2
FCB PIN CONDITION
0V to 0.75V Forced Continuous Both Controllers
(Current Reversal Allowed—
Burst Inhibited)
0.85V < V
FCB
< 6.0V Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
Feedback Resistors Regulating a Secondary Winding
>7.3V Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed No
Minimum Peak Current
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added to
the LTC3727LX-1 by loading the I
TH
pin with a resistive
divider having a Thevenin equivalent voltage source equal
to the midpoint operating voltage range of the error
amplifier, or 1.2V (see Figure 8).
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application. A
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LTC3727LX-1
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complete explanation is included in Design Solutions 10
(see www.linear.com).
Supplying INTV
CC
power through the EXTV
CC
switch
input from an output-derived source will scale the V
IN
current required for the driver and control circuits by a
factor of (Duty Cycle)/(Efficiency). For example, in a
20V to 5V application, 10mA of INTV
CC
current results
in approximately 2.5mA of V
IN
current. This reduces the
mid-current loss from 10% or more (if the driver was
powered directly from V
IN
) to only a few percent.
3. I
2
R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor, and input and output capacitor ESR. In continuous
mode the average output current flows through L and
R
SENSE
, but is “chopped” between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs
have approximately the same R
DS(ON)
, then the resis-
tance of one MOSFET can simply be summed with the
resistances of L, R
SENSE
and ESR to obtain I
2
R losses.
For example, if each R
DS(ON)
= 30mΩ, R
L
= 50mΩ,
R
SENSE
= 10mΩ and R
ESR
= 40mΩ (sum of both input
and output capacitance losses), then the total resis-
tance is 130mΩ. This results in losses ranging from 3%
to 13% as the output current increases from 1A to 5A
for a 5V output, or a 4% to 20% loss for a 3.3V output.
Efficiency varies as the inverse square of V
OUT
for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance
digital systems is not doubling but quadrupling the
importance of loss terms in the switching regulator
system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) V
IN
2
I
O(MAX)
C
RSS
f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that C
IN
has
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a mini-
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Figure 8. Active Voltage Positioning Applied to the LTC3727LX-1
I
TH
R
C
R
T1
INTV
CC
C
C
3727LX1 F08
LTC3727LX-1
R
T2
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3727LX-1 circuits: 1) LTC3727LX-1 V
IN
current (including loading on the 3.3V internal regulator),
2) INTV
CC
regulator current, 3) I
2
R losses, 4) Topside
MOSFET transition losses.
1. The V
IN
current has two components: the first is the DC
supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control cur-
rents; the second is the current drawn from the 3.3V
linear regulator output. V
IN
current typically results in a
small (<0.1%) loss.
2. INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTV
CC
to ground. The resulting dQ/dt is a current
out of INTV
CC
that is typically much larger than the
control circuit current. In continuous mode, I
GATECHG
=f(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges of the
topside and bottom side MOSFETs.
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LTC3727LXEUH-1#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual, 2-Phase Step-Down Controller in QFN
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