8
LTC3727LX-1
3727lx1fa
RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13): Combina-
tion of Soft-Start and Run Control Inputs. A capacitor to
ground at each of these pins sets the ramp time to full
output current. Forcing either of these pins back below
1.0V causes the IC to shut down the circuitry required for
that particular controller.
SENSE1
+
, SENSE2
+
(Pins 2, 14/Pins 30, 12): The (+)
Input to the Differential Current Comparators. The I
TH
pin
voltage and controlled offsets between the SENSE
–
and
SENSE
+
pins in conjunction with R
SENSE
set the current
trip threshold.
SENSE1
–
, SENSE2
–
(Pins 3, 13/Pins 31, 11): The (–)
Input to the Differential Current Comparators.
V
OSENSE1
, V
OSENSE2
(Pins 4, 12/Pins 1, 9): Receives the
remotely-sensed feedback voltage for each controller from
an external resistive divider across the output.
PLLFLTR (Pin 5/Pin 2): The phase-locked loop’s lowpass
filter is tied to this pin. Alternatively, this pin can be driven
with an AC or DC voltage source to vary the frequency of
the internal oscillator.
PLLIN (Pin 6/Pin 3): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with 50kΩ. The phase-locked loop will force the rising top
gate signal of controller 1 to be synchronized with the
rising edge of the PLLIN signal.
FCB (Pin 7/Pin 4): Forced Continuous Control Input. This
input acts on both controllers and is normally used to
regulate a secondary winding. Pulling this pin below 0.8V
will force continuous synchronous operation. Do not
leave this pin floating.
I
TH1,
I
TH2
(Pins 8, 11/Pins 5, 8): Error Amplifier Outputs
and Switching Regulator Compensation Points. Each as-
sociated channels’ current comparator trip point increases
with this control voltage.
SGND (Pin 9/Pin 6): Small Signal Ground. Common
to both controllers; must be routed separately from
high current grounds to the common (–) terminals
of the C
OUT
capacitors.
3.3V
OUT
(Pin 10/Pin 7): Linear Regulator Output.
Capable of supplying 10mA DC with peak currents as
high as 50mA.
UU
U
PI FU CTIO S
PGND (Pin 20/Pin 19): Driver Power Ground. Connects to
the sources of bottom (synchronous) N-channel MOS-
FETs, anodes of the Schottky rectifiers and the (–)
terminal(s) of C
IN
.
INTV
CC
(Pin 21/Pin 20): Output of the Internal 7.5V Linear
Low Dropout Regulator and the EXTV
CC
Switch. The driver
and control circuits are powered from this voltage source.
Must be decoupled to power ground with a minimum of 4.7µF
tantalum or other low ESR capacitor.
EXTV
CC
(Pin 22/Pin 21): External Power Input to an
Internal Switch Connected to INTV
CC
. This switch closes
and supplies V
CC
power, bypassing the internal
low drop-
out regulator, whenever EXTV
CC
is higher than 7.3V. See
EXTV
CC
connection in Applications section. Do not exceed
8.5V on this pin.
BG1, BG2 (Pins 23, 19/Pins 22, 18): High Current Gate
Drives for Bottom (Synchronous) N-Channel MOSFETs.
Voltage swing at these pins is from ground to INTV
CC
.
V
IN
(Pin 24/Pin 23): Main Supply Pin. A bypass capacitor
should be tied between this pin and the signal ground pin.
BOOST1, BOOST2 (Pins 25, 18/Pins 24, 17): Bootstrapped
Supplies to the Top Side Floating Drivers. Capacitors are
connected between the boost and switch pins and Schot-
tky diodes are tied between the boost and INTV
CC
pins.
Voltage swing at the boost pins is from INTV
CC
to (V
IN
+
INTV
CC
).
SW1, SW2 (Pins 26, 17/Pins 25, 15): Switch Node
Connections to Inductors. Voltage swing at these pins is
from a Schottky diode (external) voltage drop below
ground to V
IN
.
TG1, TG2 (Pins 27, 16/Pins 26, 14): High Current Gate
Drives for Top N-Channel MOSFETs. These are the outputs
of floating drivers with a voltage swing equal to INTV
CC
–
0.5V superimposed on the switch node voltage SW.
PGOOD (Pin 28/Pin 27): Open-Drain Logic Output. PGOOD
is pulled to ground when the voltage on either V
OSENSE
pin
is not within ±7.5% of its set point.
Exposed Pad (Pin 33, UH Package): Signal Ground. Must
be soldered to the PCB ground for electrical contact and
optimum thermal performance.
G Package/UH Package
