PCA9536 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 7 November 2017 13 of 24
NXP Semiconductors
PCA9536
4-bit I
2
C-bus and SMBus I/O port
10. Dynamic characteristics
[1] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] t
VD;DAT
= minimum time for SDA data output to be valid following SCL LOW.
[3] C
b
= total capacitance of one bus line in pF.
Table 11. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
BUF
bus free time between a STOP and
START condition
4.7 - 1.3 - s
t
HD;STA
hold time (repeated) START condition 4.0 - 0.6 - s
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - s
t
SU;STO
set-up time for STOP condition 4.0 - 0.6 - s
t
HD;DAT
data hold time 0 - 0 - s
t
VD;ACK
data valid acknowledge time
[1]
0.3 3.45 0.1 0.9 s
t
VD;DAT
data valid time
[2]
300 - 50 - ns
t
SU;DAT
data set-up time 250 - 100 - ns
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - s
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - s
t
r
rise time of both SDA and SCL signals - 1000 20 + 0.1C
b
[3]
300 ns
t
f
fall time of both SDA and SCL signals - 300 20 + 0.1C
b
[3]
300 ns
t
SP
pulse width of spikes that must be
suppressed by the input filter
- 50 - 50 ns
Port timing
t
v(Q)
data output valid time - 200 - 200 ns
t
su(D)
data input set-up time 100 - 100 - ns
t
h(D)
data input hold time 1 - 1 - s
Fig 12. Definition of timing
t
SP
t
BUF
t
HD;STA
PP S
t
LOW
t
r
t
HD;DAT
t
f
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
002aaa986
0.7 × V
DD
0.3 × V
DD
0.7 × V
DD
0.3 × V
DD
