PCA9536 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 7 November 2017 6 of 24
NXP Semiconductors
PCA9536
4-bit I
2
C-bus and SMBus I/O port
6.1.3 Register 1 - Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3.
Bit values in this register have no effect on pins defined as inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection, not the actual pin
value.
‘Not used’ bits can be programmed with either logic 0 or logic 1.
6.1.4 Register 2 - Polarity Inversion register
This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input Port data polarity is retained.
‘Not used’ bits can be programmed with either logic 0 or logic 1.
Table 6. Register 1 - Output Port register bit description
Legend: * default value
Bit Symbol Access Value Description
7 O7 R 1* not used
6O6 R 1*
5O5 R 1*
4O4 R 1*
3 O3 R 1* reflects outgoing logic levels of pins defined as
outputs by Register 3
2O2 R 1*
1O1 R 1*
0O0 R 1*
Table 7. Register 2 - Polarity Inversion register bit description
Legend: * default value
Bit Symbol Access Value Description
7 N7 R/W 0* not used
6N6 R/W 0*
5N5 R/W 0*
4N4 R/W 0*
3 N3 R/W 0* inverts polarity of Input Port register data
0 = Input Port register data retained (default
value)
1 = Input Port register data inverted
2N2 R/W 0*
1N1 R/W 0*
0N0 R/W 0*
