OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD7298BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
AD7298
Rev. B | Page 21 of 24
SERIAL INTERFACE
The
CS
going low provides the first address bit to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges, beginning with a second
address bit. Thus, the first falling clock edge on the serial clock
has the first address bit provided for reading and also clocks out
the second address bit. The three remaining address bits and
12 data bits are clocked out by subsequent SCLK falling edges.
The final bit in the data transfer is valid for reading on the
16
th
falling edge having been clocked out on the previous (15
th
)
falling edge.
Figure 30 shows the detailed timing diagram for the serial
interface to the AD7298. The serial clock provides the conver-
sion clock and controls the transfer of information to and from
the AD7298 during each conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track-and-hold into hold mode
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires 16 SCLK cycles to complete. The track-and-hold
goes back into track on the 14
th
SCLK falling edge as shown in
at Point B. On the 16
th
SCLK falling edge or on the
rising edge of
Figure 30
CS
, the DOUT line goes back into three-state.
In applications with a slower SCLK, it may be possible to read
in data on each SCLK rising edge depending on the SCLK
frequency. The first rising edge of SCLK after the
CS
falling
edge would have the first address bit provided, and the 15
th
rising SCLK edge would have last data bit provided.
If the rising edge of
CS
occurs before 16 SCLKs have elapsed,
the conversion is terminated, the DOUT line goes back into tri-
state, and the control register is not updated; otherwise, DOUT
returns to three-state on the 16
th
SCLK falling edge. Sixteen serial
clock cycles are required to perform the conversion process and
to access data from the AD7298.
Writing information to the control register takes place on the
first 16 falling edges of SCLK in a data transfer, assuming the MSB
(that is, the WRITE bit) has been set to 1. The 16-bit word read
from the AD7298 always contains four channel address bits that
the conversion result corresponds to, followed by the 12-bit
conversion result.
For the AD7298, four-channel address bits (ADD3 to ADD0)
that identify which channel the conversion result corresponds
to precede the 12 bits of data (see Table 9).
CS
DOUT
DIN
t
2
t
3
t
9
t
10
t
4
t
7
t
ACQUISITION
t
8
t
QUIET
t
5
t
6
SCLK
THREE-
STATE
THREE-
STATE
ADD3
WRITE REPEAT CH0 CH1 CH2 CH3 EXT_REF PPD
T
SENSE
AVG
ADD2
12345 1314
B
15 16
ADD1 ADD0 DB11 DB10 DB2 DB1 DB0
08754-014
Figure 30. Serial Interface Timing Diagram
AD7298
Rev. B | Page 22 of 24
TEMPERATURE SENSOR READ
The temperature sensor conversion involves two phases, the
integration phase and the conversion phase as detailed in the
Temperature Sensor Operation section. The integration phase
is initiated on the falling edge of
CS
and once completed the
conversion is automatically initiated internally by the AD7298.
When a temperature conversion integration is initiated, the
T
SENSE
_BUSY signal goes high to indicate that a temperature
conversion is in progress and remains high until the conversion
is completed.
The total time to measure and convert a temperature channel
with the AD7298 is 100 s max. Once the T
SENSE
_BUSY signal
goes low to indicate that the temperature conversion is
completed, 100 ns must elapse prior to the next falling edge
of
CS
. If a minimum of 100 ns is not adhered to between the
falling edge of T
SENSE
_BUSY and the subsequent falling edge of
CS
, the next conversion will be corrupted but the temperature
result that is framed by the
CS
will not be affected. This
restriction is in place to ensure that sufficient acquisition time
is allowed for the next conversion.
Once the T
SENSE
_BUSY signal goes high, the user may provide a
CS
falling edge to frame the read of the previous conversion and
program the control register if required (see ). Figure 31
Once the previous conversion result has been read, any
subsequent
CS
falling edges which occur while the T
SENSE
_BUSY
signal is high are internally ignored by the AD7298. If addi-
tional
CS
falling edges are provided while T
SENSE
_BUSY is high,
the AD7298 provides an invalid digital output of all 1s.
Alternatively, if
CS
remains high while T
SENSE
_BUSY is high,
then the DOUT bus remains in three-state.
If the user writes to the control register during the first 16 SCLK
cycles following T
SENSE
_BUSY going high, the configuration of
the device for the next conversion, which is initiated on the
subsequent
CS
falling edge after T
SENSE
_BUSY goes low, is
altered. If the user configures the part for partial power-down in
a write to the control register during the first 16 SCLK cycles
following T
SENSE
_BUSY going high, the temperature sensor
conversion is aborted and the part enters partial power-down
on the 16
th
SCLK falling edge.
Thus, it is recommended not to write to the control register if
the
CS
signal will be toggling while T
SENSE
_BUSY is high. Care
should be taken to ensure that the WRITE bit is set to zero
during the temperature conversion phase when
CS
is toggling.
If an SCLK frequency of more than 10 kHz is used, the
temperature conversion requires more than one standard
read cycle to complete. In this case, the user can monitor the
T
SENSE
_BUSY signal to determine when the conversion is
completed and the result is available for reading.
CS
SCLK
DOUT
DIN
112161 16 1 16
TEMPERATURE SENSOR RESULT
PREVIOUS CONVERSION
RESULT
CONFIGURE CONTROL REGISTER
FOR NEXT CONVERSION
DATA WRITTEN TO CONTROL
REGISTER CH T
SENSE
SELECTED
T
SENSE
_BUSY
THE TEMPERATURE
CONVERSION IS COMPLETED
t
11
THE TEMPERATURE
INTEGRATION BEGINS
ENSURES ADEQUATE ACQUISITION
TIME FOR NEXT ADC CONVERSION
08754-015
Figure 31. Serial Interface Timing Diagram for the Temperature Sensor Conversion
AD7298
Rev. B | Page 23 of 24
LAYOUT AND CONFIGURATION
POWER SUPPLY BYPASSING AND GROUNDING
For optimum performance, carefully consider the power supply
and ground return layout on any PCB where the AD7298 is
used. The PCB containing the AD7298 should have separate
analog and digital sections, each having its own area of the
board. The AD7298 should be located in the analog section
on any PCB.
Decouple the power supply to the AD7298 to ground with
10 µF and 0.1 µF capacitors. Place the capacitors as physically
close as possible to the device, with the 0.1 µF capacitor ideally
right up against the device. It is important that the 0.1 µF
capacitor have low effective series resistance (ESR) and low
effective series inductance (ESL); common ceramic types of
capacitors are suitable. The 0.1 µF capacitor provides a low
impedance path to ground for high frequencies caused by
transient currents due to internal logic switching. The 10 µF
capacitors are the tantalum bead type.
The power supply line should have as large a trace as possible
to provide a low impedance path and reduce glitch effects on
the supply line. Shield clocks and other components with fast
switching digital signals from other parts of the board by a
digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects on the board.
The best board layout technique is the microstrip technique
where the component side of the board is dedicated to the
ground plane only and the signal traces are placed on the solder
side; however, this is not always possible with a 2-layer board.
TEMPERATURE MONITORING
The AD7298 is ideal for monitoring the thermal environment.
The die accurately reflects the exact thermal conditions that
affect nearby integrated circuits. The AD7298 measures and
converts the temperature at the surface of its own semicon-
ductor chip.
When it is used to measure the temperature of a nearby heat
source, the thermal impedance between the heat source and the
AD7298 must be considered. When the thermal impedance is
determined, the temperature of the heat source can be inferred
from the AD7298 output.
As much as 60% of the heat transferred from the heat source to
the thermal sensor on the AD7298 die is discharged via the
copper tracks and the bond pads. Of the pads on the AD7298,
the GND pad transfers most of the heat. Therefore, to measure
the temperature of a heat source, it is recommended that the
thermal resistance between the AD7298 GND pad and the
GND of the heat source be reduced as much as possible.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD7298BCPZ

Mfr. #:
Buy AD7298BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 8-Ch 1 MSPS 10B SAR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet