LT1766/LT1766-5
16
1766fc
INPUT CAPACITOR
Step-down regulators draw current from the input supply in
pulses. The rise and fall times of these pulses are very fast.
The input capacitor is required to reduce the voltage ripple
this causes at the input of LT1766 and force the switching
current into a tight local loop, thereby minimizing EMI.
The RMS ripple current can be calculated from:
IIVVVV
RIPPLE RMS
OUT OUT IN OUT IN
()
=
()
–/
2
Ceramic capacitors are ideal for input bypassing. At 200kHz
switching frequency, the energy storage requirement of the
input capacitor suggests that values in the range of 2.2μF
to 20μF are suitable for most applications. If operation is
required close to the minimum input required by the output
of the LT1766, a larger value may be required. This is to
prevent excessive ripple causing dips below the minimum
operating voltage resulting in erratic operation.
Depending on how the LT1766 circuit is powered up you
may need to check for input voltage transients.
The input voltage transients may be caused by input volt-
age steps or by connecting the LT1766 converter to an
already powered up source such as a wall adapter. The
sudden application of input voltage will cause a large surge
of current in the input leads that will store energy in the
parasitic inductance of the leads. This energy will cause the
input voltage to swing above the DC level of input power
source and it may exceed the maximum voltage rating of
input capacitor and LT1766.
The easiest way to suppress input voltage transients is
to add a small aluminum electrolytic capacitor in parallel
with the low ESR input capacitor. The selected capacitor
needs to have the right amount of ESR in order to criti-
cally dampen the resonant circuit formed by the input lead
inductance and the input capacitor. The typical values of
ESR will fall in the range of 0.5Ω to 2Ω and capacitance
will fall in the range of 5μF to 50μF.
If tantalum capacitors are used, values in the 22μF to 470μF
range are generally needed to minimize ESR and meet
ripple current and surge ratings. Care should be taken to
ensure the ripple and surge ratings are not exceeded. The
AVX TPS and Kemet T495 series are surge rated. AVX
recommends derating capacitor operating voltage by 2:1
for high surge applications.
CATCH DIODE
Highest effi ciency operation requires the use of a Schottky
type diode. DC switching losses are minimized due to its
low forward voltage drop, and AC behavior is benign due
to its lack of a signifi cant reverse-recovery time. Schottky
diodes are generally available with reverse-voltage ratings
of up to 60V and even 100V, and are price competitive
with other types.
The use of so-called ultrafast recovery diodes is generally
not recommended. When operating in continuous mode,
the reverse-recovery time exhibited by ultrafast diodes will
result in a slingshot type effect. The power internal switch
will ramp up V
IN
current into the diode in an attempt to
get it to recover. Then, when the diode has fi nally turned
off, some tens of nanoseconds later, the V
SW
node volt-
age ramps up at an extremely high dV/dt, perhaps 5 to
even 10V/ns! With real world lead inductances, the V
SW
node can easily overshoot the V
IN
rail. This can result in
poor RFI behavior and if the overshoot is severe enough,
damage the IC itself.
The suggested catch diode (D1) is an International Rectifi er
10MQ060N Schottky. It is rated at 1.5A average forward
current and 60V reverse voltage. Typical forward voltage
is 0.63V at 1A. The diode conducts current only during
switch off time. Peak reverse voltage is equal to regulator
input voltage. Average forward current in normal operation
can be calculated from:
I
IVV
V
DAVG
OUT IN OUT
IN
()
=
()
This formula will not yield values higher than 1.5A with
maximum load current of 1.5A. The only reason to
consider a larger diode is the worst-case condition of a
high input voltage and shorted output. With a shorted
condition, diode current will increase to a typical value
of 2A, determined by peak switch current limit. This is
safe for short periods of time, but it would be prudent to
check with the diode manufacturer if continuous operation
under these conditions must be tolerated.
APPLICATIONS INFORMATION
LT1766/LT1766-5
17
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APPLICATIONS INFORMATION
BOOST PIN
For most applications, the boost components are a 0.33μF
capacitor and a 1N4148W diode. The anode is typically
connected to the regulated output voltage to generate a
voltage approximately V
OUT
above V
IN
to drive the output
stage. However, the output stage discharges the boost ca-
pacitor during the on time of the switch. The output driver
requires at least 3V of headroom throughout this period
to keep the switch fully saturated. If the output voltage is
less than 3.3V, it is recommended that an alternate boost
supply is used. The boost diode can be connected to the
input, although, care must be taken to prevent the 2× V
IN
boost voltage from exceeding the BOOST pin absolute
maximum rating. The additional voltage across the switch
driver also increases power loss, reducing effi ciency. If
available, and independent supply can be used with a local
bypass capacitor.
A 0.33μF boost capacitor is recommended for most ap-
plications. Almost any type of fi lm or ceramic capacitor
is suitable, but the ESR should be <1Ω to ensure it can
be fully recharged during the off time of the switch. The
capacitor value is derived from worst-case conditions of
4700ns on time, 42mA boost current and 0.7V discharge
ripple. The boost capacitor value could be reduced under
less demanding conditions, but this will not improve cir-
cuit operation or effi ciency. Under low input voltage and
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start-up operation.
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1766. Typically, UVLO is used in situations where
the input supply is
current limited
, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
Threshold voltage for lockout is about 2.38V. A 5.5μA
bias current fl ows
out
of the pin at this threshold. The
internally generated current is used to force a default high
state on the shutdown pin if the pin is left open. When
low shutdown current is not an issue, the error due to this
current can be minimized by making R
LO
10k or less. If
shutdown current is an issue, R
LO
can be raised to 100k,
but the error due to initial bias current and changes with
temperature should be considered.
Rk
R
RV V
VR A
LO
HI
LO IN
LO
=
()
=
()
()
10
238
238 55
to 100k 25k suggested
.
..μ
V
IN
= Minimum input voltage
+
+
2.38V
0.4V
GND
V
SW
LT1766
INPUT
R
FB
L1
C1
R
HI
1766 F04
OUTPUT
SHDN
STANDBY
IN
TOTAL
SHUTDOWN
5.5μA
R
LO
C2
+
Figure 4. Undervoltage Lockout
LT1766/LT1766-5
18
1766fc
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface ca-
pacitance to the switching nodes are minimized. If high
resistor values are used, the shutdown pin should be
bypassed with a 1000pF capacitor to prevent coupling
problems from the switch node. If hysteresis is desired
in the undervoltage lockout point, a resistor, R
FB
, can
be added to the output node. Resistor values can be
calculated from:
R
RV VV V
RA
RRV V
HI
LO IN OUT
LO
FB HI OUT
=
−+
()
+
[]
()
=
()
()
238 1
238 55
./
..
/
ΔΔ
Δ
μ
25k suggested for R
LO
V
IN
= Input voltage at which switching stops as input
voltage descends to trip level
ΔV = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if input
voltage drops below 12V and should not restart unless input
rises back to 13.5V. ΔV is therefore 1.5V and V
IN
= 12V.
Let R
LO
= 25k.
R
k
kA
k
k
Rk k
HI
FB
=
−+
()
+
[]
μ
()
=
()
=
=
()
=
25 12 2 38 1 5 5 1 1 5
238 25 55
25 10 41
224
116
116 5 1 5 387
../ .
.– .
.
.
/.
SYNCHRONIZING
The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The synchronizing range is equal
to
initial
operating frequency up to 700kHz. This means
that
minimum
practical sync frequency is equal to the
worst-case
high
self-oscillating frequency (228kHz), not
the typical operating frequency of 200kHz. Caution should
be used when synchronizing above 265kHz because at
higher sync frequencies the amplitude of the internal slope
compensation used to prevent subharmonic switching is
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insuffi cient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
At power-up, when V
C
is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows
the frequency foldback to operate in the shorted output
condition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
0.6V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maxi-
mum effi ciency, switch rise and fall times are typically
in the nanosecond range. To prevent noise both radiated
and conducted, the high speed switching current path,
shown in Figure 5, must be kept as short as possible.
This is implemented in the suggested layout of Figure 6.
Shortening this path will also reduce the parasitic trace
inductance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a fl yback spike across the
LT1766 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT1766 that may exceed its absolute
1766 F05
5V
L1
V
IN
LT1766
D1 C1C3
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
Figure 5. High Speed Switching Path
APPLICATIONS INFORMATION

LT1766EGN-5#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1.5A 200kHz High Voltage Step-down Regulator
Lifecycle:
New from this manufacturer.
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