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LT3430IFE#PBF

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LT3430/LT3430-1
16
34301fa
R
RV VV V
RA
RRV V
HI
LO IN OUT
LO
FB HI OUT
=
−+
()
+
[]
−
()
=
()
()
238 1
238 55
./
..
/
∆∆
∆
µ
25k suggested for R
LO
V
IN
= Input voltage at which switching stops as input
voltage descends to trip level
∆V = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if
input voltage drops below 12V and should not restart
unless input rises back to 13.5V. ∆V is therefore 1.5V and
V
IN
= 12V. Let R
LO
= 25k.
R
k
kA
k
k
Rk k
HI
FB
=
−+
()
+
[]
µ
()
=
()
=
=
()
=
25 12 238155 1 15
238 25 55
25 10 41
224
116
116 5 1 5 387
../ .
.– .
.
.
/.
SYNCHRONIZING
The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The LT3430 synchronizing range
is equal to initial operating frequency up to 700kHz. This
means that minimum practical sync frequency is equal to
the worst-case high self-oscillating frequency (228kHz), not
the typical operating frequency of 200kHz. Caution should
be used when synchronizing above 265kHz because at
higher sync frequencies the amplitude of the internal slope
compensation used to prevent subharmonic switching is
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insuffi cient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation. The LT3430-1 synchronizing range
is from 125kHz to 250kHz (slope compensation loss oc-
curs above 133kHz).
At power-up, when V
C
is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows
the frequency foldback to operate in the shorted output
condition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
0.6V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
APPLICATIONS INFORMATION
–
+
–
+
2.38V
0.4V
GND
V
SW
LT3430/LTC3430-1
INPUT
R
FB
R
HI
3430 F04
OUTPUT
C1
L1
SHDN
STANDBY
IN
TOTAL
SHUTDOWN
5.5
µA
R
LO
C2
+
Figure 4. Undervoltage Lockout
LT3430/LT3430-1
17
34301fa
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
effi ciency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. This is
implemented in the suggested layout of Figure 6. Shorten-
ing this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a fl yback spike across the LT3430/
LT3430-1 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT3430/LT3430-1 that may exceed its
absolute maximum rating. A ground plane should always
be used under the switcher circuitry to prevent interplane
coupling and overall noise.
APPLICATIONS INFORMATION
3430 F05
5
V
L1
V
IN
LT3430/
LT3430-1
D1C3 C1
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
GND GND1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHDN
SYNC
GND
BOOST
V
IN
V
IN
SW
SW
PLACE FEEDTHROUGH AROUND
GROUND PINS (4 CORNERS) FOR
GOOD THERMAL CONDUCTIVITY
LT3430/
LT3430-1
C3
C1
D1
C2
D2
R2
R1
3430 F06
C
FB
C
F
R
C
C
C
L1
MINIMIZE
LT3430/LT3430-1
C3-D1 LOOP
V
IN
PINS 3 AND 4
ARE SHORTED TOGETHER.
SW PINS 2 AND 5 ARE ALSO
SHORTED TOGETHER (USING
AVAILABLE SPACE UNDERNEATH
THE DEVICE BETWEEN PINS AND
GND PLANE)
GND
GND
BIAS
FB
V
C
CONNECT TO
GROUND PLANE
KELVIN SENSE
V
OUT
KEEP FB AND V
C
COMPONENTS
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
SOLDER THE EXPOSED PAD
(PIN 17) TO THE ENTIRE COPPER
GROUND PLANE UNDERNEATH
THE DEVICE. NOTE: THE BOOST
AND BIAS COPPER TRACES ARE
ON A SEPARATE LAYER FROM
THE GROUND PLANE
GND
V
OUT
V
IN
GND1
2
3
4
5
6 BOOST
V
IN
V
IN
SW
SW
LT3430/
LT3430-1
Figure 5. High Speed Switching Path
Figure 6. Suggested Layout
LT3430/LT3430-1
18
34301fa
The V
C
and FB components should be kept as far away as
possible from the switch and boost nodes. The LT3430/
LT3430-1 pinout has been designed to aid in this. The
ground for these components should be separated from
the switch current path. Failure to do so will result in poor
stability or subharmonic like oscillation.
Board layout also has a signifi cant effect on thermal
resistance. Pins 1, 8, 9 and 16, GND, should be soldered
to a continuous copper ground plane under the LT3430/
LT3430-1 die. The FE package has an exposed pad (Pin
17) which is the best thermal path for heat out of the
package. Soldering the exposed pad to the copper ground
plane under the device will reduce die temperature and
increase the power capability of the LT3430/LT3430-1. Add-
ing multiple solder fi lled feedthroughs under and around
the four corner pins to the ground plane will also help.
Similar treatment to the catch diode and coil terminations
will reduce any additional heating effects.
PARASITIC RESONANCE
Resonance or “ringing” may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schottky
diodes have very high “Q” junction capacitance that can
ring for many cycles when excited at high frequency. If
total lead length for the input capacitor, diode and switch
path is 1 inch, the inductance will be approximately 25nH.
At switch off, this will produce a spike across the NPN
output device in addition to the input voltage. At higher
currents this spike can be in the order of 10V to 20V
or higher with a poor layout, potentially exceeding the
abso
lute max switch voltage. The path around switch,
catch diode and input capacitor must be kept as short as
possible to ensure reliable operation. When looking at this,
a >100MHz oscilloscope must be used, and waveforms
should be observed on the leads of the package. This
switch off spike will also cause the SW node to go below
ground. The LT3430/LT3430-1 have special circuitry inside
which mitigates this problem, but negative voltages over
0.8V lasting longer than 10ns should be avoided. Note that
100MHz oscilloscopes are barely fast enough to see the
details of the falling edge overshoot in Figure 7.
A second, much lower frequency ringing is seen during
switch off time if load current is low enough to allow the
inductor current to fall to zero during part of the switch off
time (see Figure 8). Switch and diode capacitance reso-
nate with the inductor to form damped ringing at 1MHz
to 10MHz. This ringing is not harmful to the regulator
and it has not been shown to contribute signifi cantly to
EMI. Any attempt to damp it with a resistive snubber will
degrade effi ciency.
APPLICATIONS INFORMATION
50ns/DIV
3430 F07
2V/DIV
SW RISE SW FALL
V
IN
= 40V
V
OUT
= 5V
L = 22µH
3430 F08
1µs/DIV
10mV/DIV
SWITCH NODE
VOLTAGE
INDUCTOR
CURRENT AT
I
OUT
= 0.1A
0.2A/DIV
LT3430
Figure 7. Switch Node Resonance Figure 8. Discontinuous Mode Ringing
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LT3430IFE#PBF

Mfr. #:
Buy LT3430IFE#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi V, 3A, 200kHz Buck Sw Reg
Lifecycle:
New from this manufacturer.
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