LT3430/LT3430-1
22
34301fa
stability. This ESR, however, contributes signifi cantly to
the ripple voltage at the output (see Output Ripple Voltage
in the Applications Information section). It is possible to
reduce capacitor size and output ripple voltage by replac-
ing the tantalum output capacitor with a ceramic output
capacitor because of its very low ESR. The zero provided
by the tantalum output capacitor must now be reinserted
back into the loop. Alternatively, there may be cases where,
even with the tantalum output capacitor, an additional
zero is required in the loop to increase phase margin for
improved transient response.
A zero can be added into the loop by placing a resistor (R
C
)
at the V
C
pin in series with the compensation capacitor,
C
C
, or by placing a capacitor (C
FB
) between the output
and the FB pin.
When using R
C
, the maximum value has two limitations.
First, the combination of output capacitor ESR and R
C
may stop the loop rolling off altogether. Second, if the
loop gain is not rolled off suffi ciently at the switching
frequency, output ripple will perturb the V
C
pin enough to
cause unstable duty cycle switching similar to subharmonic
oscillations. If needed, an additional capacitor (C
F
) can be
added across the R
C
/C
C
network from the V
C
pin to ground
to further suppress V
C
ripple voltage.
With a tantalum output capacitor, the LT3430/LT3430-1
already includes a resistor (R
C
) and fi lter capacitor (C
F
)
at the V
C
pin (see Figures 10 and 11) to compensate the
loop over the entire V
IN
range (to allow for stable pulse
skipping for high V
IN
-to-V
OUT
ratios ≥ 10). A ceramic output
capacitor can still be used with a simple adjustment to the
resistor R
C
for stable operation (see Ceramic Capacitors
section for stabilizing LT3430). If additional phase margin
is required, a capacitor (C
FB
) can be inserted between the
output and FB pin but care must be taken for high output
voltage applications. Sudden shorts to the output can create
unacceptably large negative transients on the FB pin.
For V
IN
-to-V
OUT
ratios < 10, higher loop bandwidths are
possible by readjusting the frequency compensation
components at the V
C
pin.
When checking loop stability, the circuit should be operated
over the application’s full voltage, current and tempera-
ture range. Proper loop compensation may be obtained
by empirical methods as described in Application Notes
19 and 76.
CONVERTER WITH BACKUP OUTPUT REGULATOR
In systems with a primary and backup supply, for example,
a battery powered device with a wall adapter input, the
output of the LT3430/LT3430-1 can be held up by the
backup supply with the LT3430/LT3430-1 input discon-
nected. In this condition, the SW pin will source current
into the V
IN
pin. If the
S
H
D
N pin is held at ground, only the
shut down current of 30µA will be pulled via the SW pin
from the second supply. With the
S
H
D
N pin fl oating, the
APPLICATIONS INFORMATION
+
1.22V
V
SW
V
C
LT3430/LTC3430-1
GND
3430 F10
R1
OUTPUT
ESR
C
F
C
C
R
C
R
O
200k
ERROR
AMPLIFIER
FB
R2
C1
R
LOAD
CURRENT MODE
POWER STAGE
g
m
= 2mho
g
m
=
2000µmho
+
TANTALUM
ESL
C1
CERAMIC
C
FB
FREQUENCY (Hz)
GAIN (dB)
80
60
40
20
0
–20
–40
PHASE (DEG)
180
150
120
90
60
30
0
3430 F11
GAIN
PHASE
10
V
IN
= 42V
V
OUT
= 5V
I
LOAD
= 1A
C
OUT
= 100µF, 10V, 0.1
1k 10k 1M100 100k
R
C
= 3.3k
C
C
= 22nF
C
F
= 220pF
Figure 10. Model for Loop Response Figure 11. Overall Loop Response
LT3430/LT3430-1
23
34301fa
APPLICATIONS INFORMATION
LT3430/LT3430-1 will consume their quiescent operating
current of 1.5mA. The V
IN
pin will also source current to
any other components connected to the input line. If this
load is greater than 10mA or the input could be shorted to
ground, a series Schottky diode must be added, as shown
in Figure 12. With these safeguards, the output can be held
at voltages up to the V
IN
absolute maximum rating.
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 13 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
confi guration with the addition of R3, R4, C
SS
and Q1. As
the output starts to rise, Q1 turns on, regulating switch
current via the V
C
pin to maintain a constant dv/dt at the
output. Output rise time is controlled by the current through
C
SS
defi ned by R4 and Q1’s V
BE
. Once the output is in
regulation, Q1 turns off and the circuit operates normally.
R3 is transient protection for the base of Q1.
Rise Time
RC V
V
SS OUT
BE
=
()( )( )
4
Using the values shown in Figure 10,
Rise Time ms=
()( )
()
=
47 10 15 10 5
07
5
39
••
.
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can
be used for sequencing multiple regulator outputs.
5V, 2A
REMOVABLE
INPUT
C2
0.68µF
C
F
220pF
54k
D1
30BQ060
3430 F12
C3
4.7µF
R
C
3.3k
C
C
0.022µF
D3
30BQ060
D2
MMSD914TI
33µH
C1
100µF
10V
ALTERNATE
SUPPLY
25k
R1
15.4k
R2
4.99k
BOOST
V
IN
LT3430
SHDN
SYNC
SW
BIAS
FB
V
C
GND
+
OUTPUT
5V
2A
INPUT
40V
3430 F13
C2
0.68µF
C1
100µF
10V
C
SS
15nF
C
F
220pF
D1
30BQ060
OR B250A
C3
4.7µF
50V
CER
D2
MMSD914TI
L1
33µH
R1
15.4k
R3
2k
C
C
0.022µF
R2
4.99k
R4
47k
L1: CDRH104R-220M
Q1
BOOST BIAS
V
IN
LT3430
SHDN
SYNC
SW
FB
V
C
GND
+
R
C
3.3k
Figure 12. Dual Source Supply with 25µA Reverse Leakage
Figure 13. Buck Converter with Adjustable Soft-Start
LT3430/LT3430-1
24
34301fa
DUAL OUTPUT SEPIC CONVERTER
The circuit in Figure 14 generates both positive and negative
5V outputs with a single piece of magnetics. The two induc-
tors shown are actually just two windings on a standard
Coiltronics inductor. The topology for the 5V output is a
standard buck converter. The – 5V topology would be a
simple fl yback winding coupled to the buck converter if
C4 were not present. C4 creates a SEPIC (single-ended
primary inductance converter) topology which improves
regulation and reduces ripple current in L1. Without C4,
the voltage swing on L1B compared to L1A would vary
due to relative loading and coupling losses. C4 provides a
low impedance path to maintain an equal voltage swing in
L1B, improving regulation. In a fl yback converter, during
switch on time, all the converter’s energy is stored in L1A
only, since no current fl ows in L1B. At switch off, energy
is transferred by magnetic coupling into L1B, powering
the –5V rail. C4 pulls L1B positive during switch on time,
causing current to fl ow, and energy to build in L1B and
C4. At switch off, the energy stored in both L1B and C4
supply the –5V rail. This reduces the current in L1A and
changes L1B current waveform from square to triangular.
For details on this circuit, including maximum output cur-
rents, see Design Note 100.
POSITIVE-TO-NEGATIVE CONVERTER
The circuit in Figure 15 is a positive-to-negative topology
using a grounded inductor. It differs from the standard
approach in the way the IC chip derives its feedback
signal because the LT3430/LT3430-1 accepts only posi-
tive feedback signals. The ground pin must be tied to the
regulated negative output. A resistor divider to the FB pin
then provides the proper feedback voltage for the chip.
The following equation can be used to calculate maximum
load current for the positive-to-negative converter:
I
I
VV
VVfL
VV
VV VV
MAX
P
IN OUT
OUT IN
OUT IN
OUT IN OUT F
=
+
++
()( )
()()()
()(.)
(–.)()
2
015
015
I
P
= Maximum rated switch current
V
IN
= Minimum input voltage
V
OUT
= Output voltage
V
F
= Catch diode forward voltage
0.15 = Switch voltage drop at 3A
Example: with V
IN(MIN)
= 5.5V, V
OUT
= 12V, L = 10µH,
V
F
= 0.52V, I
P
= 3A: I
MAX
= 0.6A.
V
OUT
5V
V
OUT
–5V
* L1 IS A SINGLE CORE WITH TWO WINDINGS
COILTRONICS #CTX25-4A
IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: 30BQ060
V
IN
7.5V TO 60V
GND
3430 F14
C2
0.68µF
C
F
220pF
D1
C1
100µF
10V TANT
C5
100µF
10V TANT
C3
4.7µF
100V
CERAMIC
C4
100µF
10V
TANT
D2
MMSD914TI
D3
L1A*
25µH
L1B*
R1
15.4k
R2
4.99k
++
+
R
C
3.3k
C
C
0.022µF
BOOST
V
IN
LT3430
SHDN
SYNC
SW
FB
V
C
GND
APPLICATIONS INFORMATION
Figure 14. Dual Output SEPIC Converter

LT3430IFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi V, 3A, 200kHz Buck Sw Reg
Lifecycle:
New from this manufacturer.
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