LT3430/LT3430-1
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THERMAL CALCULATIONS
Power dissipation in the LT3430/LT3430-1 chip comes
from four sources: switch DC loss, switch AC loss, boost
circuit current, and input quiescent current. The follow-
ing formulas show how to calculate each of these losses.
These formulas assume continuous mode operation, so
they should not be used for calculating effi ciency at light
load currents.
Switch loss:
P
RI V
V
tIVf
SW
SW OUT OUT
IN
EFF OUT IN
=
()( )
+
()()()
2
12(/ )
(Note: Switching losses are less for the LT3430-1 oper-
ating at only 100kHz)
Boost current loss:
P
VI
V
BOOST
OUT OUT
IN
=
()
2
36/
Quiescent current loss:
PV V
Q IN OUT
=
()
+
()
0 0015 0 003..
R
SW
= Switch resistance (≈0.15) hot
t
EFF
= Effective switch current/voltage overlap time
= (t
r
+ t
f
+ t
Ir
+ t
If
)
t
r
= (V
IN
/1.2)ns
t
f
= (V
IN
/1.1)ns
t
Ir
= t
If
= (I
OUT
/0.2)ns
f = Switch frequency
Example: with V
IN
= 40V, V
OUT
= 5V and I
OUT
= 2A:
P
W
PW
PW
SW
BOOST
Q
=
( )()()
+
()
()
()( )
()
=+=
=
()
()
=
=+=
015 2 5
40
90 10 1 2 2 40 200 10
008 072 08
5236
40
004
40 0 0015 5 0 003 0 08
2
93
2
.
•/
...
/
.
(. ) (. ) .
Total power dissipation in the IC is given by:
P
TOT
= P
SW
+ P
BOOST
+ P
Q
= 0.8W + 0.04W + 0.08W = 0.92W
Thermal resistance for the LT3430/LT3430-1 package is in-
uenced by the presence of internal or backside planes.
TSSOP (Exposed Pad) Package: With a full plane under
the TSSOP package, thermal resistance will be about
45°C/W.
To calculate die temperature, use the proper thermal
resistance number for the desired package and add in
worst-case ambient temperature:
T
J
= T
A
+ (θ
JA
• P
TOT
)
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power:
P
VV V I
V
DIODE
F IN OUT LOAD
IN
=
( )( )( )
V
F
= Forward voltage of diode (assume 0.52V at 2A)
PW
DIODE
==
(. )( – )()
.
052 40 5 2
40
091
P
INDUCTOR
= (I
LOAD
)
2
(R
IND
)
R
IND
= Inductor DC resistance (assume 0.1Ω)
P
INDUCTOR
(2)
2
(0.1) = 0.4W
Only a portion of the temperature rise in the external
inductor and diode is coupled to the junction of the
LT3430. Based on empirical measurements, the thermal
effect on the LT3430 junction temperature due to power
dissipation in the external inductor and catch diode can
be calculated as:
∆T
J
(LT3430) ≈ (P
DIODE
+ P
INDUCTOR
)(5°C/W)
Using the example calculations for LT3430 dissipation, the
LT3430 die temperature will be estimated as:
T
J
= T
A
+ (θ
JA
• P
TOT
) + [5 • (P
DIODE
+ P
INDUCTOR
)]
With the TSSOP package (θ
JA
= 45°C/W), at an ambient
temperature of 50°C:
T
J
= 50 + (45 • 0.92) + (5 • 1.31) = 98°C
Die temperature can peak for certain combinations of V
IN
,
V
OUT
and load current. While higher V
IN
gives greater
switch AC losses, quiescent and catch diode losses, a
APPLICATIONS INFORMATION
LT3430/LT3430-1
20
34301fa
lower V
IN
may generate greater losses due to switch DC
losses. In general, the maximum and minimum V
IN
levels
should be checked with maximum typical load current for
calculation of the LT3430/LT3430-1 die temperature. If a
more accurate die temperature is required, a measure-
ment of the SYNC pin resistance (to GND) can be used.
The SYNC pin resistance can be measured by forcing a
voltage no greater than 0.5V at the pin and monitoring the
pin current over temperature in an oven. This should be
done with minimal device power (low V
IN
and no switching
(V
C
= 0V)) in order to calibrate SYNC pin resistance with
ambient (oven) temperature.
Note: Some of the internal power dissipation in the IC,
due to BOOST pin voltage, can be transferred outside
of the IC to reduce junction temperature, by increasing
the voltage drop in the path of the boost diode D2 (see
Figure 9). This reduction of junction temperature inside
the IC will allow higher ambient temperature operation for
a given set of conditions. BOOST pin circuitry dissipates
power given by:
P
VI V
V
DISS
OUT SW C
IN
BOOST Pin =
()
•/36
2
Typically V
C2
(the boost voltage across the capacitor C2)
equals V
OUT
. This is because diodes D1 and D2 can be
considered almost equal, where:
V
C2
= V
OUT
– V
FD2
– (–V
FD1
) = V
OUT
Hence the equation used for boost circuitry power dissi-
pation given in the previous Thermal Calculations section
is stated as:
P
VI
V
V
DISS BOOST
OUT SW
IN
OUT()
•/
=
()
36
Here it can be seen that boost power dissipation increases
as the square of V
OUT
. It is possible, however, to reduce
V
C2
below V
OUT
to save power dissipation by increasing the
voltage drop in the path of D2. Care should be taken that
V
C2
does not fall below the minimum 3.3V boost voltage
required for full saturation of the internal power switch.
For output voltages of 5V, V
C2
is approximately 5V. During
switch turn on, V
C2
will fall as the boost capacitor C2 is
dicharged by the BOOST pin. In the previous BOOST Pin
section, the value of C2 was designed for a 0.7V droop in
V
C2
= V
DROOP
. Hence, an output voltage as low as 4V would
still allow the minimum 3.3V for the boost function using
the C2 capacitor calculated. If a target output voltage of
12V is required, however, an excess of 8V is placed across
the boost capacitor which is not required for the boost
function but still dissipates additional power.
What is required is a voltage drop in the path of D2 to
achieve minimal power dissipation while still maintaining
minimum boost voltage across C2. A zener, D4, placed in
series with D2 (see Figure 9), drops voltage to C2.
Example : the BOOST pin power dissipation for a 20V input
to 12V output conversion at 2A is given by:
PW
BOOST
=
()
=
12 2 36 12
20
04
•/
.
If a 7V zener D4 is placed in series with D2, then power
dissipation becomes :
PW
BOOST
=
()
=
12 2 36 5
20
0 167
•/
.
For an FE package with thermal resistance of 45°C/W,
ambient temperature savings would be, T(ambient) sav-
APPLICATIONS INFORMATION
BOOST
V
IN
D1
R1
V
OUT
C
F
C
C
LT3430/
LT3430-1
SHDN
SYNC
SW
BIAS
FB
V
C
GND
C2
C1
L1
D2
R2
3430 F09
C3
V
IN
D2 D4
+
R
C
Figure 9. BOOST Pin, Diode Selection
LT3430/LT3430-1
21
34301fa
ings = 0.233W • 45°C/W = 11°C. The 7V zener should be
sized for excess of 0.233W operaton. The tolerances of
the zener should be considered to ensure minimum V
C2
exceeds 3.3V + V
DROOP
.
Input Voltage vs Operating Frequency Considerations
The absolute maximum input supply voltage for the LT3430/
LT3430-1 is specifi ed at 60V. This is based solely on internal
semiconductor junction breakdown effects. Due to internal
power dissipation, the actual maximum V
IN
achievable in
a particular application may be less than this.
A detailed theoretical basis for estimating internal power
loss is given in the section, Thermal Considerations. Note
that AC switching loss is proportional to both operating
frequency and output current. The majority of AC switching
loss is also proportional to the square of input voltage.
For example, while the combination of V
IN
= 40V, V
OUT
= 5V at 2A and f
OSC
= 200kHz may be easily achievable,
simultaneously raising V
IN
to 60V and f
OSC
to 700kHz is
not possible. Nevertheless, input voltage transients up to
60V can usually be accommodated, assuming the result-
ing increase in internal dissipation is of insuffi cient time
duration to raise die temperature signifi cantly.
A second consideration is controllability. A potential limita-
tion occurs with a high step-down ratio of V
IN
to V
OUT
, as
this requires a correspondingly narrow minimum switch
on time. An approximate expression for this (assuming
continuous mode operation) is given as follows:
min t
VV
Vf
ON
OUT F
IN OSC
=
+
()
where:
V
IN
= input voltage
V
OUT
= output voltage
V
F
= Schottky diode forward drop
f
OSC
= switching frequency
A potential controllability problem arises if the LT3430/
LT3430-1 are called upon to produce an on time shorter
than it is able to produce. Feedback loop action will lower
then reduce the V
C
control voltage to the point where
some sort of cycle-skipping or odd/even cycle behavior
is exhibited.
In summary:
1. Be aware that the simultaneous requirements of high
V
IN
, high I
OUT
and high f
OSC
may not be achievable in
practice due to internal dissipation. The Thermal Con-
siderations section offers a basis to estimate internal
power. In questionable cases a prototype supply should
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high V
IN
, low V
OUT
and
high f
OSC
can result in an unacceptably short minimum
switch on time. Cycle skipping and/or odd/even cycle
behavior will result although correct output voltage is
usually maintained. The LT3430-1 100kHz switching
frequency will allow higher V
IN
/V
OUT
ratios without
pulse skipping.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the
worse the board layout, the more diffi cult the circuit will
be to stabilize. This is true of almost all high frequency
analog circuits, read the Layout Considerations section
rst. Common layout errors that appear as stability prob-
lems are distant placement of input decoupling capacitor
and/or catch diode, and connecting the V
C
compensation
to a ground track carrying signifi cant switch current. In
addition, the theoretical analysis considers only fi rst
order non-ideal component behavior. For these reasons,
it is important that a fi nal stability check is made with
production layout and components.
The LT3430/LT3430-1 use current mode control. This al-
leviates many of the phase shift problems associated with
the inductor. The basic regulator loop is shown in Figure
10. The LT3430/LT3430-1 can be considered as two g
m
blocks, the error amplifi er and the power stage.
Figure 11 shows the overall loop response. At the V
C
pin, the frequency compensation components used are:
R
C
= 3.3k, C
C
= 0.022µF and C
F
= 220pF. The output
capacitor used is a 100µF, 10V tantalum capacitor with
typical ESR of 100mΩ. LT3430-1 uses two of these
capacitors in parallel.
The ESR of the tantalum output capacitor provides a use-
ful zero in the loop frequency response for maintaining
APPLICATIONS INFORMATION

LT3430IFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi V, 3A, 200kHz Buck Sw Reg
Lifecycle:
New from this manufacturer.
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