OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

CY62187EV30LL-55BAXI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
CY62187EV30 MoBL
®
Document Number: 001-48998 Rev. *K Page 10 of 19
Figure 6. Write Cycle 1 (WE Controlled)
[23, 24, 25, 26]
Figure 7. Write Cycle 2 (CE
1
or CE
2
Controlled)
[23, 24, 25, 26]
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
t
BW
NOTE 26
ADDRESS
WE
DATA I/O
OE
BHE
/
BLE
CE
1
CE
2
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
NOTE 26
t
BW
t
SA
ADDRESS
WE
DATA I/O
OE
BHE/BLE
CE
1
CE
2
Notes
23. The internal Write time of the memory is defined by the overlap of WE
, CE
1
= V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
24. Data I/O is high impedance if OE
= V
IH
.
25. If CE
1
goes HIGH and CE
2
goes LOW simultaneously with WE = V
IH
, the output remains in a high impedance state.
26. During this period the I/Os are in output state and input signals should not be applied.
CY62187EV30 MoBL
®
Document Number: 001-48998 Rev. *K Page 11 of 19
Figure 8. Write Cycle 3 (WE Controlled, OE LOW)
[27, 28, 29]
Figure 9. Write Cycle 4 (BHE/BLE Controlled, OE LOW)
[27, 28]
Switching Waveforms (continued)
DATA
IN
VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
t
BW
NOTE 28
ADDRESS
CE
1
CE
2
BHE/BLE
WE
DATA I/O
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
DATA
IN
VALID
t
BW
t
SCE
t
PWE
NOTE 28
ADDRESS
CE
1
CE
2
BHE/BLE
WE
DATA I/O
Notes
27. If CE
1
goes HIGH and CE
2
goes LOW simultaneously with WE = V
IH
, the output remains in a high impedance state.
28. During this period the I/Os are in output state and input signals should not be applied.
29. The minimum write cycle pulse width should be equal to the sum of t
SD and tHZWE.
CY62187EV30 MoBL
®
Document Number: 001-48998 Rev. *K Page 12 of 19
Truth Table
CE
1
CE
2
WE OE BHE BLE Inputs Outputs Mode Power
HX
[30]
XXX
[30]
X
[30]
High Z Deselect/Power Down Standby (I
SB
)
X
[30]
LXXX
[30]
X
[30]
High Z Deselect/Power Down Standby (I
SB
)
X
[30]
X
[30]
X X H H High Z Deselect/Power Down Standby (I
SB
)
L H H L L L Data Out (I/O
0
–I/O
15
) Read Active (I
CC
)
L H H L H L High Z (I/O
8
–I/O
15
);
Data Out (I/O
0
–I/O
7
)
Read Active (I
CC
)
L H H L L H Data Out (I/O
8
–I/O
15
);
High Z (I/O
0
–I/O
7
)
Read Active (I
CC
)
L H L X L L Data In (I/O
0
–I/O
15
) Write Active (I
CC
)
LHLXHLHigh Z (I/O
8
–I/O
15
);
Data In (I/O
0
–I/O
7
)
Write Active (I
CC
)
L H L X L H Data In (I/O
8
–I/O
15
);
High Z (I/O
0
–I/O
7
)
Write Active (I
CC
)
L H H H L H High Z Output Disabled Active (I
CC
)
L H H H H L High Z Output Disabled Active (I
CC
)
L H H H L L High Z Output Disabled Active (I
CC
)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

CY62187EV30LL-55BAXI

Mfr. #:
Buy CY62187EV30LL-55BAXI
Manufacturer:
Cypress Semiconductor
Description:
SRAM 64Mb 3V 55ns 4M x 16 LP SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet