AD7747ARUZ-REEL7 Datasheet AD7747ARUZ-REEL7, AD7747ARUZ, AD7747ARUZ-REEL | P19-P21

AD7747

Rev. 0 | Page 18 of 28

CONFIGURATION REGISTER

Address Pointer 0x0A, Default Value 0xA0

Converter update rate and mode of operation setup.

Table 17. Configuration Register Bit Map

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic VTFS1 VTFS0 CAPFS2 CAPFS1 CAPFS0 MD2 MD1 MD0

Default 0 0 0 0 0 0 0 0

Table 18.

Bit Mnemonic Description

Voltage/temperature channel digital filter setup—conversion time/update rate setup.

VTCHOP = 1

VTFS1 VTFS0 Conversion Time (ms) Update Rate (Hz) −3 dB Frequency (Hz)

0 0 20.1 49.8 26.4

0 1 32.1 31.2 15.9

1 0 62.1 16.1 8.0

VTFS1

VTFS0

1 1 122.1 8.2 4.0

Capacitive channel digital filter setup—conversion time/update rate setup.

CAPFS2 CAPFS1 CAPFS0 Conversion Time (ms) Update Rate −3 dB Frequency (Hz)

0 0 0 22.0 45.5 43.6

0 0 1 23.9 41.9 39.5

0 1 0 40.0 25.0 21.8

0 1 1 76.0 13.2 10.9

1 0 0 124.0 8.1 6.9

1 0 1 154.0 6.5 5.3

1 1 0 184.0 5.5 4.4

CAPFS2

CAPFS1

CAPFS0

1 1 1 219.3 4.6 4.0

Converter mode of operation setup.

MD2 MD1 MD0 Mode

0 0 0 Idle

0 0 1 Continuous conversion

0 1 0 Single conversion

0 1 1 Power-down

1 0 0 –

1 0 1 Capacitance system offset calibration

1 1 0 Capacitance or voltage system gain calibration

MD2

MD1

MD0

1 1 1 –

AD7747

Rev. 0 | Page 19 of 28

CAP DAC A REGISTER

Address Pointer 0x0B, Default Value 0x00

Capacitive DAC setup.

Table 19. Cap DAC A Register Bit Map

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic DACAENA – DACA—6-Bit Value

Default 0 0 0x00

Table 20.

Bit Mnemonic Description

7 DACAENA DACAENA = 1 connects capacitive DACA to the positive capacitance input.

6 – This bit must be 0 for proper operation.

5 to 1 DACA

DACA value, Code 0x00 ≈ 0 pF, Code 0x3F ≈ full range.

CAP DAC B REGISTER

Address Pointer 0x0C, Default Value 0x00

Capacitive DAC setup.

Table 21. Cap DAC B Register Bit Map

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic DACBENB – DACB—6-Bit Value

Default 0 0 0x00

Table 22.

Bit Mnemonic Description

7 DACBENB DACBENB = 1 connects capacitive DACB to the negative capacitance input.

6 – This bit must be 0 for proper operation.

5 to 1 DACB

DACB value, Code 0x00 ≈ 0 pF, Code 0x3F ≈ full range.

AD7747

Rev. 0 | Page 20 of 28

CAP OFFSET CALIBRATION REGISTER

16 Bits, Address Pointer 0x0D, 0x0E,

Default Value 0x8000

The capacitive offset calibration register holds the capacitive

channel zero-scale calibration coefficient. The coefficient is

used to digitally remove the capacitive channel offset. The

of a capacitance offset calibration. The capacitive offset calibra-

tion resolution (cap offset register LSB) is less than 32 aF; the

full range is ±1 pF.

CAP GAIN CALIBRATION REGISTER

16 Bits, Address Pointer 0x0F, 0x10,

Default Value 0xXXXX

Capacitive gain calibration register. The register holds the

capacitive channel full-scale factory calibration coefficient.

VOLT GAIN CALIBRATION REGISTER

16 Bits, Address Pointer 0x11,0x12,

Default Value 0xXXXX

Voltage gain calibration register. The register holds the voltage

channel full-scale factory calibration coefficient.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

AD7747ARUZ-REEL7

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Manufacturer:

Analog Devices Inc.

Description:

Data Acquisition ADCs/DACs - Specialized 24Bit w/ Temp Sensr

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AD7747ARUZ-REEL7

AD7747ARUZ-REEL7

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