AD7747
Rev. 0 | Page 4 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
Normal Mode Rejection
5
75 dB 50 Hz ± 1%, conversion time = 122.1 ms
50 dB 60 Hz ± 1%, conversion time = 122.1 ms
Common-Mode Rejection
2
95 dB V
IN
= 1 V
INTERNAL VOLTAGE REFERENCE
Voltage 1.169 1.17 1.171 V T
A
= 25°C
Drift vs. Temperature 5 ppm/°C
EXTERNAL VOLTAGE REFERENCE INPUT
Differential REFIN Voltage
2
0.1 2.5 V
DD
V
Absolute REFIN Voltage
2
GND − 0.03 V
DD
+ 0.03 V
Average REFIN Input Current 400 nA/V
Average REFIN Input Current Drift ±50 pA/V/°C
Common-Mode Rejection 80 dB
SERIAL INTERFACE LOGIC INPUTS (SCL, SDA)
V
IH
Input High Voltage 2.1 V
V
IL
Input Low Voltage 0.8 V
Hysteresis 150 mV
Input Leakage Current (SCL) ±0.1 ±1 μA
OPEN-DRAIN OUTPUT (SDA)
V
OL
Output Low Voltage 0.4 V I
SINK
= −6.0 mA
I
OH
Output High Leakage Current 0.1 1 μA V
OUT
= V
DD
LOGIC OUTPUT (
RDY
)
V
OL
Output Low Voltage 0.4 V I
SINK
= 1.6 mA, V
DD
= 5 V
V
OH
Output High Voltage 4.0 V I
SOURCE
= 200 μA, V
DD
= 5 V
V
OL
Output Low Voltage 0.4 V I
SINK
= 100 μA, V
DD
= 3 V
V
OH
Output High Voltage V
DD
− 0.6 V I
SOURCE
= 100 μA, V
DD
= 3 V
POWER REQUIREMENTS
V
DD
-to-GND Voltage 4.75 5.25 V V
DD
= 5 V, nominal
2.7 3.6 V V
DD
= 3.3 V, nominal
I
DD
Current 850 μA Digital inputs equal to V
DD
or GND
750 μA V
DD
= 5 V
700 μA V
DD
= 3.3 V
I
DD
Current Power-Down Mode 0.5 2 μA Digital inputs equal to V
DD
or GND
1
Capacitance units: 1 pF = 10
−12
F; 1 fF = 10
−15
F; 1 aF = 10
−18
F. Full scale (FS) = 8.192 pF; full-scale range (FSR) = ±8.192 pF.
2
Specification is not production tested, but is supported by characterization data at initial product release.
3
Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C.
At different temperatures, compensation for gain drift over temperature is required.
4
The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register
LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter +
system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF; the larger
offset can be removed using CAPDACs.
5
Specification is not production tested, but guaranteed by design.
6
The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.
7
The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance.
8
Using an external temperature sensing diode 2N3906, with nonideality factor n
f
= 1.008, connected as in Figure 37, with total serial resistance <100 Ω.
9
Full-scale error applies to both positive and negative full scale.
