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Overview
The W158 is designed to provide the essential frequency
sources to work with advanced multiprocessing Intel archi-
tecture platforms. Split voltage supply signaling provides 2.5V
and 3.3V clock frequencies operating up to 133 MHz.
From a low-cost 14.31818-MHz reference crystal oscillator,
the W158 generates 2.5V clock outputs to support CPUs, core
logic chip set, and Direct RDRAM clock generators. It also
provides skew-controlled PCI and IOAPIC clocks
synchronous to CPU clock, 48-MHz Universal Serial Bus
(USB) clock, and replicates the 14.31818-MHz reference
clock.
All CPU, PCI, and IOAPIC clocks can be synchronously
modulated for spread spectrum operations. Cypress employs
proprietary techniques that provide the maximum EMI
reduction while minimizing the clock skews that could reduce
system timing margins. Spread Spectrum modulation is
enabled by the active LOW control signal SPREAD#.
The W158 also includes power management control inputs. By
using these inputs, system logic can stop CPU and/or PCI
clocks or power down the entire device to conserve system
power.
Pin Definitions
Pin Name Pin No.
Pin
Type Pin Description
CPU0:3 41, 42, 45, 46 O CPU Clock Outputs 0 through 3: These four CPU clocks run at a frequency set by
SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2.
CPUdiv2_ 0:1 49, 50 O Synchronous Memory Reference Clock Output 0 through 1: Reference clock for
Direct RDRAM clock generators running at 1/2 CPU clock frequency. Output voltage
swing is set by the voltage applied to VDDQ2.
PCI1:7 9, 11, 12, 14,
15, 17, 18
O PCI Clock Outputs 1 through 7: These seven PCI clock outputs run synchronously to
the CPU clock. Voltage swing is set by the power connection to VDDQ3. PCI1:7 outputs
are stopped when PCI _STOP# is held LOW.
PCI_F 8 O PCI_F (PCI Free-running): This PCI clock output runs synchronously to the CPU clock.
Voltage swing is set by the power connection to VDDQ3. PCI_F is not affected by the
state of PCI_STOP#.
REF0:1 2, 3 O 14.318-MHz Reference Clock Output: 3.3V copies of the 14.318-MHz reference clock.
IOAPIC0:2 53, 54, 55 O I/O APIC Clock Output: Provides 16.67-MHz fixed frequency. The output voltage swing
is set by the power connection to VDDQ2.
48MHz 30 O 48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by voltage
applied to VDDQ3.
3V66_0:3 21, 22, 25, 26 O 66-MHz Output 0 through 3: Fixed 66-MHz outputs. Output voltage swing is controlled
by voltage applied to VDDQ3.
SEL0:1 32, 33 I Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting clock output
modes.
SEL133/100# 28 I Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output
frequency as shown in Table 1.
X1 5 I Crystal Connection or External Reference Frequency Input: Connect to either a
14.318-MHz crystal or an external reference signal.
X2 6 O Crystal Connection: An output connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
SPREAD# 34 I Active LOW Spread Spectrum Enable: 3.3V LVTTL-compatible input that enables
spread spectrum mode when held LOW.
PWRDWN# 35 I Active LOW Power Down Input: 3.3V LVTTL-compatible asynchronous input that
requests the device to enter power-down mode.
CPU_STOP# 36 I Active LOW CPU Clock Stop: 3.3V LVTTL-compatible asynchronous input that stops all
CPU and 3V66 clocks when held LOW. CPUdiv2 outputs are unaffected by this input.
PCI_STOP# 37 I Active LOW PCI Clock Stop: 3.3V LVTTL-compatible asynchronous input that stops all
PCI outputs except PCI_F when held LOW.
VDDQ3 4, 10, 16, 23,
27, 31, 39
P Power Connection: Power supply for PCI output buffers, 48-MHz USB output buffer,
Reference output buffers, 3V66 output buffers, core logic, and PLL circuitry. Connect to
3.3V supply.
VDDQ2 43, 47, 51, 56 P Power Connection: Power supply for IOAPIC, CPU, and CPUdiv2 output buffers.
Connect to 2.5V supply.
GND 1, 7, 13, 19,
20, 24, 29, 38,
40, 44, 48, 52
G Ground Connection: Connect all ground pins to the common system ground plane.
