... Document #: 38-07164 Rev. *A Page Page 10 of 12 of 12
2.5V AC Electrical Characteristics
T
A
= 0°C to +70°C, V
DDQ3
= 3.3V±5%, V
DDQ2
= 2.5V±5%
f
XTL
= 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
[38]
Note:
38.Period, Jitter, offset, and skew measured on rising edge at 1.25V.
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
Parameter Description Test Condition/Comments
CPU = 133 MHz CPU = 100 MHz
UnitMin. Typ. Max. Min. Typ. Max.
t
P
Period Measured on rising edge at 1.25V 7.5 7.65 10 10.2 ns
t
H
High Time Duration of clock cycle above 2.0V 1.87 3.0 ns
t
L
Low Time Duration of clock cycle below 0.4V 1.67 2.8 ns
t
R
Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns
t
F
Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns
t
D
Duty Cycle Measured on rising and falling edge at
1.25V
45 55 45 55 %
t
JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V.
Maximum difference of cycle time
between two adjacent cycles.
150 150 ps
t
SK
Output Skew Measured on rising edge at 1.25V 175 175 ps
f
ST
Frequency Stabili-
zation from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
33ms
Z
o
AC Output Impedance Average value during switching
transition. Used for determining series
termination value.
20 20
CPUdiv2 Clock Outputs, CPUdiv2_0:1 (Lump Capacitance Test Load = 20 pF)
Parameter Description Test Condition/Comments
CPU = 133 MHz CPU = 100 MHz
UnitMin. Typ. Max. Min. Typ. Max.
t
P
Period Measured on rising edge at 1.25V 15 15.3 20 20.4 ns
t
H
High Time Duration of clock cycle above 2.0V 5.25 7.5 ns
t
L
Low Time Duration of clock cycle below 0.4V 5.05 7.3 ns
t
R
Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns
t
F
Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns
t
D
Duty Cycle Measured on rising and falling edge at
1.25V
45 55 45 55 %
t
JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V.
Maximum difference of cycle time
between two adjacent cycles.
250 250 ps
t
SK
Output Skew Measured on rising edge at 1.25V 175 175 ps
f
ST
Frequency Stabili-
zation from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
33ms
Z
o
AC Output Impedance Average value during switching
transition. Used for determining series
termination value.
20 20
