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72V3653L15PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
16
COMMERCIAL TEMPERATURE RANGE
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
TM
WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
Figure 4. Partial Reset (IDT Standard and FWFT Modes)
NOTES:
1. PRS must be HIGH during Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 3. Reset and Loading X and Y with a Preset Value of Eight (IDT Standard and FWFT Modes)
t
RSF
CLKA
RS1, RS2
FF/IR
AE
AF
MBF1,
MBF2
CLKB
EF/OR
FS2,
FS1,FS0
4662 drw 05
t
RSTS
t
RSTH
t
FSH
t
FSS
t
WFF
t
REF
(2)
t
RSF
0,1
t
RSF
BEBE/FWFT
FWFT
t
BES
1
2
t
FWS
t
BEH
t
WFF
RTM LOW
CLKA
PRS
FF/IR
AE
AF
MBF1,
CLKB
EF/OR
4662 drw 06
t
RSTS
t
RSTH
t
WFF
t
WFF
t
REF
t
RSF
t
RSF
t
RSF
MBF2
(2)
RTM LOW
NOTES:
1. RS1 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
17
COMMERCIAL TEMPERATURE RANGE
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
TM
WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
NOTE:
1. CSA = LOW, W/RA = HIGH, MBA = LOW.
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT
Modes)
NOTES:
1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FF/IR is set HIGH.
2. Programmable offsets are written serially to the SD input in the order AF offset (Y) and AE offset (X).
4662 drw 07
CLKA
RS1
FF/IR
A0-A35
FS1,FS0
ENA
t
FSH
t
WFF
t
ENH
t
ENS2
t
DS
t
DH
4
0,0
AF Offset
(
Y
)
AE Offset
(X)
First Word to FIFO1
t
FSH
t
FSS
FS2
t
FSS
1
2
CLKA
FF/IR
t
SENS
t
SENH
FS0/SD
(2)
t
SPH
t
SENS
t
SENH
t
FSS
t
WFF
FS1/SEN
AE Offset
(
X
)
LSB
t
SDS
t
SDH
t
SDS
t
SDH
AF Offset
(
Y
)
MSB
RS1
4
t
FSS
t
FSH
FS2
4662 drw 08
18
COMMERCIAL TEMPERATURE RANGE
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
TM
WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
NOTE:
1. Data read from the FIFO
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 8. Port B Long-Word Read Cycle (IDT Standard and FWFT Modes)
SIZE MODE
(1)
DATA WRITTEN TO FIFO DATA READ FROM FIFO
(SELECT AT RESET)
BM SIZE BE A35-A27 A26-A18 A17-A9 A8-A0 B35-B27 B26-B18 B17-B9 B8-B0
LXXA B C D A B C D
DATA SIZE TABLE FOR FIFO LONG-WORD READS
NOTE:
1. Written to FIFO.
Figure 7. Port A Write Cycle Timing for FIFO (IDT Standard and FWFT Modes)
4662 drw09
CLKA
FF/IRA
ENA
A0-A35
MBA
CSA
W/RA
t
CLKH
t
CLKL
t
CLK
t
ENS1
t
ENS1
t
ENS2
t
ENS2
t
DS
t
ENH
t
ENH
t
ENH
t
ENH
t
DH
W1
(1)
W2
(1)
t
ENS2
t
ENH
t
ENH
t
ENS2
No Operation
HIGH
4662 drw 10
CLKB
EF/OR
ENB
MBB
CSB
W/RB
t
DIS
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
A
t
MDV
t
EN
t
A
t
ENS2
t
ENH
t
ENS2
t
ENH
W1
(1)
W2
(1)
W3
(1)
t
ENH
t
DIS
t
EN
W2
(1)
(1)
W1Previous Data
t
MDV
t
A
OR
B0-B35
(Standard Mode)
B0-B35
(FWFT Mode)
t
A
No Operation
HIGH
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

72V3653L15PF8

Mfr. #:
Buy 72V3653L15PF8
Manufacturer:
IDT
Description:
FIFO UNIDIRECTIONAL/ BU 2KX36X2
Lifecycle:
New from this manufacturer.
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