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72V3653L15PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
28
COMMERCIAL TEMPERATURE RANGE
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
TM
WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
Figure 21. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36 Synchronous FIFO Memory with
Programmable Flags used in Depth Expansion Configuration
NOTES:
1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)
2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.
3. The amount of time it takes for EF/OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the
sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK, where N is the number of FIFOs in the expansion and TRCLK is the CLKB period.
4. The amount of time it takes for FF/IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
(N - 1)*(3*transfer clock) + 2*TWCLK, where N is the number of FIFOs in the expansion and TWCLK is the CLKA period.
DATA IN (Dn)
READ CLOCK (CLKB)
READ ENABLE (ENB)
EMPTY FLAG/
OUTPUT READY (EF/OR)
CHIP SELECT (CSB)
DATA OUT (Qn)
TRANSFER CLOCK
4662 drw23
IDT
72V3653
72V3663
72V3673
VCC
IDT
72V3653
72V3663
72V3673
WRITE
READ
A
0
-A
35
MBA
CHIP SELECT (CSA)
WRITE SELECT (W/RA)
WRITE ENABLE (ENA)
ALMOST-FULL FLAG (AF)
FULL FLAG/
INPUT READY (FF/IR)
WRITE CLOCK (CLKA)
CLKB
EF/OR
ENB
CSB
B
0
-B
35
W/RB
MBB
CLKA
ENA
FF/IR
CSA
MBA
A
0
-A
35
W/RA
READ SELECT (W/RB)
ALMOST-EMPTY FLAG (AE)
B
0
-B
35
MBB
VCC
n
n
n
Qn
Dn
VCC
VCC
29
COMMERCIAL TEMPERATURE RANGE
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
TM
WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
4662 drw 24
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
330
Ω
3.3 V
510
Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
GND
Timing
Input
Data,
Enable
Input
GND
3 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3 V
GND
GND
3 V
1.5 V
1.5 V
1.5 V
1.5 V
t
W
Output
Enable
Low-Level
Output
High-Level
Output
3 V
OL
GND
≈ 3 V
1.5 V
1.5 V
1.5 V
1.5 V
OH
≈ OV
GND
OH
OL
1.5 V
1.5 V
1.5 V
1.5 V
Input
In-Phase
Output
High-Level
Input
Low-Level
Input
V
V
V
V
1.5 V
3 V
t
S
t
h
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PD
t
PD
(1)
NOTE:
1. Includes probe and jig capacitance.
Figure 22. Load Circuit and Voltage Waveforms.
30
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753
San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com
www.idt.com
ORDERING INFORMATION
BLANK
4662 drw 25
Commercial (0
o
C to +70
o
C)
XXXXXX
Device Type
XXX X
Power Speed Package
X
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
Commercial Only
Process/
Temperature
Range
X
X
G
PF
L
10
15
Green
Thin Quad Flat Pack (TQFP, PK128)
Low Power
16,384 x 36 x 2 ⎯ 3.3V SyncBiFIFO with Bus-Matching
32,768 x 36 x 2 ⎯ 3.3V SyncBiFIFO with Bus-Matching
65,536 x 36 x 2 ⎯ 3.3V SyncBiFIFO with Bus-Matching
BLANK
8
Tray
Tape and Reel
72V3653
72V3663
72V3673
NOTES:
1. Industrial temperature range is available by special order.
2. Green parts available. For specific speeds and packages contact your sales office.
DATASHEET DOCUMENT HISTORY
06/23/2000 pgs. 1-5, 7-9, 11, 12, 14, 17, 18, 21-26, 28 and 29.
09/27/2001 pgs. 5, 6, 7, 8, 9, 12 and 30.
11/03/2003 pg. 1.
02/05/2009 pgs. 1 and 30.
05/13/2016 pgs. 1-3 and 30.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

72V3653L15PF8

Mfr. #:
Buy 72V3653L15PF8
Manufacturer:
IDT
Description:
FIFO UNIDIRECTIONAL/ BU 2KX36X2
Lifecycle:
New from this manufacturer.
Delivery:
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