MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
______________________________________________________________________________________ 13
Automatic Pulse-Skipping Switchover
In normal operation, the MAX1761s PWM control algo-
rithm automatically skips pulses at light loads.
Comparators at each CS_ input in the MAX1761 trun-
cate the low-side switchs on-time at the point where
the inductor current drops to zero. This occurs when
the inductor current is operating at the boundary
between continuous and discontinuous conduction
mode (Figure 4). This threshold is equal to 1/2 the
peak-to-peak ripple current, which is inversely propor-
tional to the inductor value:
where K is the on-time scale factor listed in Table 3. For
example, in the typical application circuit (Figure 1),
with V
OUT1
= 2.5V, V+ = 15V, L = 9µH, and K =
2.857µs (Table 3), switchover to pulse-skipping opera-
tion occurs at I
LOAD
= 0.33A or about 1/8 full load. The
crossover point occurs at an even lower value if a
swinging (soft-saturation) inductor is used.
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation; this is a normal operating condition that
improves light-load efficiency. Trade-offs in PFM noise
vs. light-load efficiency are made by varying the induc-
tor value. Generally, lower inductor values produce a
broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response (especially at low input-voltage levels).
Forced PWM Operation (ON2 floating)
The low-noise, forced-PWM mode (ON2 floating) dis-
ables the zero-crossing current comparator that con-
trols the low-side switch on-time. The resulting low-side
gate-drive waveform is forced to become the comple-
ment of the high-side gate-drive waveform. This, in turn,
causes the inductor current to reverse at light loads as
the PWM loop strives to maintain a constant duty ratio
of V
OUT
/V+. The benefit of forced-PWM mode is that it
keeps the switching frequency nearly constant, but it
results in a higher no-load battery current that can be
10mA to 40mA, depending on the gate capacitance of
the external MOSFETs.
Forced-PWM mode is most useful for reducing audio-
frequency noise, improving load-transient response,
and providing sink-current capability for dynamic out-
put voltage adjustment. Multiple-output applications
that use a flyback transformer or coupled inductor also
benefit from forced-PWM operation because the contin-
uous switching action improves cross-regulation.
Low-Side Current-Limit Sensing
The current-limit circuit employs a unique valley cur-
rent-sensing algorithm that uses the on-state resistance
of the low-side MOSFET as a current-sensing element.
If the current-sense signal is above the current-limit
threshold, the PWM is not allowed to initiate a new
cycle (Figure 5). The actual peak current is greater than
the current-limit threshold by an amount equal to the
inductor ripple current. Therefore, the exact current-
limit characteristic and maximum load capability are a
function of the MOSFET on-resistance, inductor value,
and input voltage. The reward for this uncertainty is
robust, lossless overcurrent sensing. When combined
with the undervoltage protection circuit, this current-
limit method is effective in almost every circumstance.
There is also a negative current limit that prevents
excessive reverse inductor currents when V
OUT
is sink-
ing current (forced PWM mode only). The negative cur-
rent-limit threshold is set to approximately 120% of the
positive current limit.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signals seen by CS_. Mount or place the IC
close to the low-side MOSFET with short, direct traces,
making a Kelvin-sense connection to the source and
drain terminals.
If greater current-limit accuracy is desired, CS can be
connected to an external sense resistor inserted
between the source of the low-side switch and ground
(Figure 6). The resulting current limit will be ILIM = 0.1V
/ R
SENSE
, and it will have ±8% error.
I
KV
2L
V+-V
V+
LOAD(SKIP)
OUT
OUT
×
INDUCTOR CURRENT
I
LOAD
= I
PEAK
/2
ON-TIME0 TIME
-I
PEAK
L
V + -V
OUT
i
t
=
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
14 ______________________________________________________________________________________
MOSFET Gate Drivers
The DH and DL outputs are optimized for driving mod-
erate-sized power MOSFETs. The MOSFET drive capa-
bility is stronger for the low-side switch. This is
consistent with the low duty factor seen in the notebook
computer environment where a large V+ to V
OUT
differ-
ential exists. An adaptive dead-time circuit monitors the
DL output and prevents the high-side FET from turning
on until DL is fully off. There must be a low-resistance,
low-inductance path from the DL driver to the MOSFET
gate for the adaptive dead-time circuit to work properly.
Otherwise, the sense circuitry in the MAX1761 will inter-
pret the MOSFET gate as off while there is still charge
left on the gate. Use very short, wide traces measuring
10 to 20 squares or less (50mils to 100mils wide if the
MOSFET is 1 inch from the device). Similar to the DL
output, an adaptive dead-time circuit also monitors the
DH output and prevents the low-side FET from turning
on until DH is fully off. The same considerations should
be used for routing the DH signal to the high-side FET.
Since the transition time for a P-channel switch can be
much longer than an N-channel switch, the dead time
prior to the high-side PMOS turning on will be more
pronounced than in other synchronous step-down reg-
ulators, which use high-side N-channel switches. On
the high-to-low transition, the voltage on the inductors
"switched" terminal flies below ground until the low-side
switch turns on. A similar dead-time spike occurs on
the opposite low-to-high transition. Depending upon the
magnitude of the load current, these spikes usually
have a minor impact on efficiency.
The high-side drivers (DH_) swing from V+ to GND and
will typically source/sink 0.6A from the gate of the P-
channel MOSFET. The low-side driver (DL_) swings
from VL to ground and will typically source 0.5A and
sink 0.9A from the gate of the N-channel FET.
The internal pulldown transistors that drive DL low are
robust, with a 2.0 (typ) on-resistance. This helps pre-
vent DL from being pulled up when the high-side
switch turns on, due to capacitive coupling from the
drain to the gate of the low-side MOSFET. This places
some restrictions on the FETs that can be used. Using
a low-side FET with smaller gate-to-drain capacitance
can prevent these problems.
Shutdown and Mode Control Inputs
The MAX1761 has two inputs (ON1, ON2) that control
the operating modes of the two regulators. Asserting
ON1 low places both regulators in micropower shut-
down mode, in which both VL and REF are disabled.
When ON1 is high, OUT1 is enabled, with VL and REF
active. ON2 serves a dual function: it is a shutdown
control for OUT2, and it determines the switching mode
for both regulators. When ON2 is low (ON2 < 0.5V),
OUT2 is disabled and OUT1 operates in normal mode.
Floating ON2 places both outputs in forced PWM
mode. When ON2 is high (2V < ON2 < V
L
), both regula-
tors run in normal operating mode. Toggling ON1 from
low to high resets the fault latch (Table 4).
Output Undervoltage Protection
The output undervoltage protection function is similar to
foldback current limiting but employs a timer rather
than a variable current limit. If the MAX1761 output volt-
age is under 70% (typ) of the nominal output voltage
20ms after coming out of shutdown, then both PWMs
are latched off and will not restart until V+ is cycled or
ON1 is toggled low to high.
INDUCTOR CURRENT
I
LIMIT
I
LOAD
0 TIME
I
PEAK
Figure 5. Valley Current-Limit Threshold Point
Figure 6. Using a Low-Side Current-Sense Resistor
DL
OUT
CS
DH
FB
V+
V
OUT
MAX1761
MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
______________________________________________________________________________________ 15
Thermal Fault Protection
The MAX1761 features a thermal fault protection circuit.
When the temperature rises above +160°C, the DL low-
side gate-driver outputs latch high until ON1 is toggled
or V+ is cycled. The fault threshold has 10°C of thermal
hysteresis, which prevents the regulator from restarting
until the die cools off.
POR and Soft-Start
Power-on reset (POR) occurs when V+ falls below
approximately 2V, resetting the fault latch and prepar-
ing the PWM for operation once the power is cycled. VL
undervoltage lockout (UVLO) circuitry inhibits switching
and forces the DL gate driver low until VL rises above
4.25V, whereupon an internal digital soft-start timer
begins to ramp up the maximum allowed current limit.
The ramp occurs in five steps: 20%, 40%, 60%, 80%,
and 100%; 100% current is available after 1.7ms.
Design Procedure
Firmly establish the input voltage range and the maxi-
mum load current before choosing the inductor operat-
ing point (ripple current ratio). The following three
factors determine the SMPS design using the
MAX1761:
1) Input Voltage Range. The maximum value
(V+(max)) must accommodate the worst-case high
AC adapter voltage. The minimum value (V+(min))
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery selec-
tor switches. If there is a choice at all, lower input
voltages result in better efficiency.
2) Maximum Load Current. There are two values to
consider, the peak load current (I
LOAD(MAX)
) and
the continuous load current (I
LOAD
). The peak load
current determines the instantaneous component
stresses and filtering requirements and thus drives
output capacitor selection, inductor saturation rat-
ing, and the design of the current-limit circuit. The
continuous load current determines the thermal
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components. Modern notebook CPUs gen-
erally exhibit I
LOAD
= I
LOAD(MAX)
80%.
3) Inductor Operating Point. This choice provides
trade-offs between size and efficiency. Low induc-
tor values cause large ripple currents, resulting in
the smallest size, but poor efficiency and high out-
put noise. The minimum practical inductor value is
one that causes the circuit to operate at the edge of
critical conduction (where the inductor current just
touches zero with every cycle at maximum load).
Inductor values lower than this grant no further size-
reduction benefit.
The MAX1761s pulse-skipping algorithm initiates skip
mode at the critical conduction point. So, the inductor
operating point also determines the load-current value
at which PWM/skip mode switchover occurs. The opti-
mum point is usually found between 20% and 50% rip-
ple current.
The inductor ripple current also impacts transient-
response performance, especially at low V
IN
- V
OUT
dif-
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The amount of output sag is also a function of the maxi-
mum duty factor, which can be calculated from the on-
time and minimum off-time:
Inductor Selection
The switching frequency (on-time) and operating point
(% ripple or LIR) determine the inductor value as fol-
lows:
Example: I
LOAD(MAX)
= 2.5A, V+(max) = 20V, V
OUT1
=
2.5V, f = 350kHz, 35% ripple current or LIR = 0.35:
L
V(- )
V+ LIR I
OUT OUT
LOAD(MAX)
=
+
×ƒ× ×
VV
V
(I ) L
2C - V
SAG
LOAD(MAX)
F (MIN) OUT
2
=
×
×+
DUTY V()
Table 4. Operating Mode Control Summary
MODE ON1 ON2 DESCRIPTION
Shutdown ON1 < 0.5V X Both OUT1 and OUT2 off, VL and REF disabled
ON1 Enabled 2.0V < ON1 < V+ ON2 < 0.5V
OUT1 on in normal mode, OUT2 off
Forced PWM 2.0V < ON1 < V+ Floating Both OUT1 and OUT2 on in forced PWM mode
Normal Operation 2.0V < ON1 < V+ 2.0V < ON2 VL Both OUT1 and OUT2 on in normal mode

MAX1761EEE-T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Controllers
Lifecycle:
New from this manufacturer.
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