MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
20 ______________________________________________________________________________________
tolerances and internal propagation delays introduce
an error to the t
ON
K-factor. Also, keep in mind that
transient response performance of buck regulators
operated close to dropout is poor, and bulk output
capacitance must often be added (see the V
SAG
equa-
tion in Design Procedure).
Dropout design example: V
IN
= 6.5V (min), V
OUT
=
5V, f = 350kHz, 250kHz. The required duty is (V
OUT
+
V
SW
) / (V+ - V
SW
) = (5V + 0.1V) / (6.5V - 0.1V) = 79.7%.
The worst-case on-time for f = 350kHz is (V
OUT
+ 0.1V)
/ V+
✕
K = 5.1V / 6.5V
✕
2.857µs-V
✕
90% = 2.017µs.
The IC duty-factor limitation is:
Thus, operation at 350kHz meets the required duty
cycle. A similar analysis with f = 250kHz (K = 4µs-V)
shows that at f = 250kHz, the maximum duty cycle is
85.0%, also meeting the required duty cycle.,
Remember to include inductor resistance and MOSFET
on-state voltage drops (V
SW
) when doing worst-case
dropout duty-factor calculations.
Fixed Output Voltages
The MAX1761’s dual-mode operation allows the selec-
tion of common voltages without requiring external
components (Figure 11). Connect FB1 to GND for a
fixed +2.5V output at OUT1; otherwise, connect FB1 to
a resistive voltage-divider for an adjustable output.
Connect FB2 to GND for a +1.8V output; otherwise,
connect FB2 to a resistive voltage-divider for an
adjustable output.
Adjusting VOUT
The output voltage can be adjusted with a resistive volt-
age-divider if desired (Figure 12). The equation for
adjusting the output voltage is:
where V
FB
is 1.0V, and R2 is about 10kΩ.
Low Input Voltage Operation (V+ = +5V)
The MAX1761 can be used in applications using a 5V
±10% input supply by overdriving VL with the input
supply voltage, V+. This not only enables operation of
the MAX1761 down to V+ = 4.5V but has the added
benefit of increasing overall efficiency. Overdriving the
VL regulator will increase the drive on the low-side
MOSFETs, thereby lowering their R
DS(ON)
and reduc-
ing power consumption. Note that VL should not be
higher than 5.5V if connected to VL. Also note, V+
should not be brought below 5V unless VL is connect-
ed directly to V+.
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. This is
especially true for dual converters, where one channel
can affect the other. The switching power stages
require particular attention (Figure 13). Refer to the
MAX1761 EV kit data sheet for a specific layout exam-
ple. If possible, mount all of the power components on
the top side of the board with their ground terminals
flush against one another. Follow these guidelines for
good PC board layout:
• Isolate the top-side power components from the
sensitive analog components on the bottom side
with a ground shield. Use a separate PGND plane
under the OUT1 and OUT2 sides (called PGND1
and PGND2). Avoid the introduction of AC currents
into the PGND1 and PGND2 ground planes. Run
the power plane ground currents on the top side
only, if possible.
• Use a star ground connection on the power plane
to minimize the crosstalk between OUT1 and OUT2.
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
• Connect AGND and PGND together close to the IC.
Do not connect them together anywhere else.
Carefully follow the grounding instructions under
Step 4 of the Layout Procedure.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance caus-
es a measurable efficiency penalty.
• CS_ and PGND connections to the synchronous
rectifiers for current limiting must be made using
Kelvin sensed connections to guarantee the cur-
rent-limit accuracy. With SO-8 MOSFETs, this is
best done by routing power to the MOSFETs from
outside, using the top copper layer, while connect-
ing PGND and CS_ inside (underneath) the SO-8
package.
.
.
