MAX1761
Small, Dual, High-Efficiency
Buck Controller for Notebooks
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where:
For a typical 350kHz application, the ESR zero frequen-
cy must be well below 100kHz, preferably below
50kHz. Tantalum and OS-CON capacitors have typical
ESR zero frequencies of 15kHz. Sanyo POS capacitors
have typical ESR zero frequencies of 20kHz. In the
design example used for inductor selection, the ESR
needed to support 50mVp-p ripple is 50mV / LIR(2.5A)
= 57.1mΩ. A single150µF/6.3V Sanyo POS capacitor
provides 55mΩ (max) ESR. This ESR results in a zero at
19.3kHz, well within the bounds of stability.
Don’t put high-value ceramic capacitors directly across
the fast feedback inputs (FB_/OUT_ to GND) without
taking precautions to ensure stability. Large ceramic
capacitors can have a high-ESR zero frequency and
may cause erratic, unstable operation. However, it’s
easy to add enough series resistance by placing the
capacitors a couple of inches downstream from the
junction of the inductor and FB_/OUT_ pin.
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and fast-feed-
back loop instability.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there isn’t enough volt-
age ramp in the output voltage signal. This “fools” the
error comparator into triggering a new cycle immedi-
ately after the 500ns minimum off-time period has
expired. Double-pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability, which is caused by insufficient ESR. Loop
instability can result in oscillations at the output after
line or load perturbations that can cause the output
voltage to go outside the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient (refer to the
MAX1761 EV kit manual) and carefully observe the out-
put voltage ripple envelope for overshoot and ringing. It
can help to simultaneously monitor the inductor current
with an AC current probe. Don’t allow more than one
cycle of ringing after the initial step-response under- or
overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (I
RMS
) imposed by the switching currents.
Nontantalum chemistries (ceramic, aluminum, or OS-
CON) are preferred due to their resilience to power-up
surge currents.
Power MOSFET Selection
DC bias and output power considerations dominate the
selection of the power MOSFETs used with the
MAX1761. Care should be taken not to exceed the
device’s maximum voltage ratings. In general, both
switches are exposed to the supply voltage, so select
MOSFETs with V
DS(MAX)
greater than V+(max). Gate
drive to the N-channel and P-channel MOSFETs is not
symmetrical. The N-channel device is driven from
ground to the logic supply VL. The P-channel device is
driven from V+ to ground. The maximum rating for V
GS
for the N-channel device is usually not an issue.
However, V
GS(MAX)
for the P-channel must be at least
V+(max). Since V
GS(MAX)
is usually lower than
V
DS(MAX)
, gate-drive constraints often dictate the
required P-channel breakdown rating.
For moderate input-to-output differentials, the high-side
MOSFET (Q1) can be sized smaller than the low-side
MOSFET (Q2) without compromising efficiency. The
high-side switch operates at a very low duty cycle
under these conditions, so most conduction losses
occur in Q2. For maximum efficiency, choose a high-
side MOSFET (Q1) that has conduction losses (I
2
RD)
equal to the switching losses (fCV+
2
). Make sure that
the conduction losses at the minimum input voltage
don’t exceed the package thermal limits or violate the
overall thermal budget. Similarly check for rating viola-
tions for conduction and switching losses at the maxi-
mum input voltage (see MOSFET Power Dissipation).
The MAX1761 has an adaptive dead-time circuitry that
prevents the high-side and low-side MOSFETs from
conducting at the same time (see MOSFET Gate
Drivers). Even with this protection, it is still possible for
delays internal to the MOSFET to prevent one MOSFET
from turning off when the other is turned on. The maxi-
mum mismatch time that can be tolerated is 60ns.
Select devices that have low turn-off times, and make
sure that NFET(t
DOFF(MAX)
) - PFET(t
DON(MIN)
) < 60ns,
and PFET(t
DOFF(MAX)
) - NFET(t
DON(MIN)
) < 60ns.
Failure to do so may result in efficiency-killing shoot-
through currents.
MOSFET selection also affects PC board layout. There
are four possible combinations of MOSFETs that can
be used with this switcher. The designs include:
• Two dual complementary MOSFETs (Figure 7)
