Field-Programmable, Chopper-Stabilized,
Unipolar Hall-Effect Switches
A3250
and
A3251
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Application Information
For additional general application information, visit the Allegro
MicroSystems Web site at www. allegromicro.com.
Typical application circuit
Typical Application Circuit
It is strongly recommended that an external ceramic bypass
capacitor, C
BYP
, in the range of 0.01 μF to 0.1 μF be connected
between the VCC pin and the supply and GND pin to reduce
both external noise and noise generated by the chopper-stabiliza-
tion technique. (The diagram at the right shows C
BYP
at 0.1 μF.)
C
BYP
should be installed so that the traces that connect it to the
A3250/A3251 are no greater than 5 mm in length. (For program-
ming the device, the capacitor may be further away from the
device, including mounting on the board used for programming
the device.)
The series resistor R
S
, in combination with C
BYP
creates a filter
for EMI pulses. (Additional information on EMC is provided
on the Allegro MicroSystems Web site.) R
S
will have a drop
of approximately 800 mV. This must be taken into consider-
ation when determining the minimum VCC requirement for the
A3250/A3251. The pull-up resistor, R
L
, should be chosen to
limit the current through the output transistor; do not exceed the
maximum continuous output current of the device.
GND
A3250/A3251
VCC
V
Supply
0.1 μF
A
R
L
C
BYP
R
S
100 Ω
1.2 kΩ
5V
VOUT
A
A
Maximum separation 5 mm
from C
BYP
to device
Field-Programmable, Chopper-Stabilized,
Unipolar Hall-Effect Switches
A3250
and
A3251
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Power Derating
The device must be operated below the maximum junction
temperature of the device, T
J(max)
. Under certain combinations of
peak conditions, reliable operation may require derating sup-
plied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating T
J
. (Thermal data is also available on
the Allegro MicroSystems Web site.)
The Package Thermal Resistance, R
JA
, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, R
JC
, is
relatively small component of R
JA
. Ambient air temperature,
T
A
, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, P
D
), can
be estimated. The following formulas represent the fundamental
relationships used to estimate T
J
, at P
D
.
P
D
= V
IN
×
I
IN
(1)
T = P
D
×
R
JA
(2)
T
J
= T
A
+ ΔT (3)
For example, given common conditions such as: T
A
= 25°C,
V
CC
= 12 V, I
CC
= 4 mA, and R
JA
= 165 °C/W, then:
P
D
= V
CC
×
I
CC
= 12 V
×
4 mA = 48 mW
T = P
D
×
R
JA
= 48 mW
×
165 °C/W = 8°C
T
J
= T
A
+ T = 25°C + 8°C = 33°C
A worst-case estimate, P
D(max)
, represents the maximum allow-
able power level (V
CC(max)
, I
CC(max)
), without exceeding T
J(max)
,
at a selected R
JA
and T
A
.
Example: Reliability for V
CC
at T
A
=
150°C, package UA, using
minimum-K PCB.
Observe the worst-case ratings for the device, specifically:
R
JA
=
165°C/W, T
J(max)
=
165°C, V
CC(max)
=
24 V, and
I
CC(max)
=
10
mA.
Calculate the maximum allowable power level, P
D(max)
. First,
invert equation 3:
T
max
= T
J(max)
– T
A
= 165
°C
150
°C = 15
°C
This provides the allowable increase to T
J
resulting from internal
power dissipation. Then, invert equation 2:
P
D(max)
= T
max
÷ R
JA
= 15°C ÷ 165 °C/W = 91 mW
Finally, invert equation 1 with respect to voltage:
V
CC(est)
= P
D(max)
÷ I
CC(max)
= 91 mW ÷ 10 mA = 9 V
The result indicates that, at T
A
, the application and device can
dissipate adequate amounts of heat at voltages V
CC(est)
.
Compare V
CC(est)
to V
CC(max)
. If V
CC(est)
V
CC(max)
, then reli-
able operation between V
CC(est)
and V
CC(max)
requires enhanced
R
JA
. If V
CC(est)
V
CC(max)
, then operation between V
CC(est)
and
V
CC(max)
is reliable under these conditions.
Field-Programmable, Chopper-Stabilized,
Unipolar Hall-Effect Switches
A3250
and
A3251
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Package LT, 3-Pin SOT89
Parting
Line
2.24
1.14
321
A
A
Active Area Depth, 0.78 mm REF
B
C
D
C
2X 1.50 BSC
4.50±0.10
1.50±0.10
0.50±0.06
0.42±0.06
1.73
+0.10
–0.11
2.20
+0.09
–0.07
2.45
+0.15
–0.16
4.10
+0.15
–0.16
1.00
+0.20
–0.11
0.40
+0.04
–0.05
Branding scale and appearance at supplier discretion
Hall element, not to scale
Reference land pattern layout (reference IPC7351 SOT89N);
All pads a minimum of 0.20 mm from all adjacent pads;
adjust as necessary to meet application process
requirements and PCB layout tolerances
Standard Branding Reference View
NNT
1
= Supplier emblem
N = Last two digits of device part number
T = Temperature code
For Reference Only; not for tooling use (reference JEDEC. TO-243AA)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
1.50
1.00
0.80
2.60
2.00
2.50
0.70
4.60
B
PCB Layout Reference View
Basic pads for low-stress, not self-aligning
Additional pad for low-stress, self-aligning
Additional area for IPC reference layout

A3251LLTTR-T

Mfr. #:
Manufacturer:
Description:
MAGNETIC SWITCH UNIPOLAR SOT89-3
Lifecycle:
New from this manufacturer.
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