13
1615J–PLD–01/06
ATF1502ASV
10. Timing Model
Figure 10-1. Timing Model
11. Input Test Waveforms and Measurement Levels
Figure 11-1. Input Test Waveforms and Measurement Levels
t
R
, t
F
= 1.5 ns typical
12. Output AC Test Loads
Figure 12-1. Output AC Test Loads
Input
Delay
t
IN
Switch
Matrix
t
UIM
Foldback Term
Delay
t
SEXP
Register Control
Delay
t
LAC
t
IC
t
EN
Logic Array
Delay
t
LAD
Global Control
Delay
t
GLOB
Internal Output
Enable Delay
t
IOE
Cascade Logic
Delay
t
PEXP
Fast Input
Delay
t
FIN
Register
Delay
t
SU
t
H
t
PRE
t
CLR
t
RD
t
COMB
t
FSU
t
FH
Output
Delay
t
OD1
t
OD2
t
OD3
t
XZ
t
ZX1
t
ZX2
t
ZX3
I/O
Delay
t
IO
R1 = 703
3.0V
OUTPUT
PIN
CL = 35 pFR2 = 8060
14
1615J–PLD–01/06
ATF1502ASV
13. AC Characteristics
Table 13-1. AC Characteristics
(1)
Symbol Parameter
-15 -20
UnitsMin Max Min Max
t
PD1
Input or Feedback to Non-registered Output 3 15 20 ns
t
PD2
I/O Input or Feedback to Non-registered Feedback 3 12 16 ns
t
SU
Global Clock Setup Time 11 16 ns
t
H
Global Clock Hold Time 0 0 ns
t
FSU
Global Clock Setup Time of Fast Input 3 3 ns
t
FH
Global Clock Hold Time of Fast Input 1 1.5 MHz
t
COP
Global Clock to Output Delay 8 10 ns
t
CH
Global Clock High Time 5 6 ns
t
CL
Global Clock Low Time 5 6 ns
t
ASU
Array Clock Setup Time 4 4 ns
t
AH
Array Clock Hold Time 4 5 ns
t
ACOP
Array Clock Output Delay 15 20 ns
t
ACH
Array Clock High Time 6 8 ns
t
ACL
Array Clock Low Time 6 8 ns
t
CNT
Minimum Clock Global Period 13 16 ns
f
CNT
Maximum Internal Global Clock Frequency 76.9 66 MHz
t
ACNT
Minimum Array Clock Period 13 16 ns
f
ACNT
Maximum Internal Array Clock Frequency 76.9 66 MHz
f
MAX
Maximum Clock Frequency 100 83.3 MHz
t
IN
Input Pad and Buffer Delay 2 2 ns
t
IO
I/O Input Pad and Buffer Delay 2 2 ns
t
FIN
Fast Input Delay 2 2 ns
t
SEXP
Foldback Term Delay 8 10 ns
t
PEXP
Cascade Logic Delay 1 1 ns
t
LAD
Logic Array Delay 6 7 ns
t
LAC
Logic Control Delay 6 7 ns
t
IOE
Internal Output Enable Delay 3 3 ns
t
OD1
Output Buffer and Pad Delay
(Slow slew rate = OFF;
V
CC
= 3.3V; C
L
= 35 pF)
55ns
t
ZX1
Output Buffer Enable Delay
(Slow slew rate = OFF;
V
CCIO
= 5.0V; C
L
= 35 pF)
79ns
t
ZX2
Output Buffer Enable Delay
(Slow slew rate = OFF;
V
CCIO
= 3.3V; C
L
= 35 pF)
79ns
15
1615J–PLD–01/06
ATF1502ASV
Notes: 1. See ordering information for valid part numbers.
t
ZX3
Output Buffer Enable Delay
(Slow slew rate = ON;
V
CCIO
= 5.0V/3.3V; C
L
= 35 pF)
10 11 ns
t
XZ
Output Buffer Disable Delay (C
L
= 5 pF) 6 7 ns
t
SU
Register Setup Time 4 5 ns
t
H
Register Hold Time 4 5 ns
t
FSU
Register Setup Time of Fast Input 2 2 ns
t
FH
Register Hold Time of Fast Input 2 2 ns
t
RD
Register Delay 1 2 ns
t
COMB
Combinatorial Delay 1 2 ns
t
IC
Array Clock Delay 6 7 ns
t
EN
Register Enable Time 6 7 ns
t
GLOB
Global Control Delay 1 1 ns
t
PRE
Register Preset Time 4 5 ns
t
CLR
Register Clear Time 4 5 ns
t
UIM
Switch Matrix Delay 2 2 ns
t
RPA
Reduced-power Adder
(2)
13 14 ns
Table 13-1. AC Characteristics (Continued)
(1)
Symbol Parameter
-15 -20
UnitsMin Max Min Max

ATF1502ASV-20JI44

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
CPLD - Complex Programmable Logic Devices ASICS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union