MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
______________________________________________________________________________________ 11
To improve the input signal bandwidth under AC condi-
tions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance and settle
quickly. For example, the MAX4265 can be used for +5V
unipolar devices, or the MAX4350 can be used for ±5V
bipolar inputs.
The T/H aperture delay is typically 13ns. Figure 2 shows
a simplified equivalent input circuit, illustrating the ADC’s
sampling architecture.
Input Bandwidth
The input tracking circuitry has a 10MHz small-signal
bandwidth, making it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Input Range and Protection
These devices provide ±10V, ±5V or 0 to +5V analog
input voltage ranges. Figure 2 shows the typical input cir-
cuit. Overvoltage protection circuitry at the analog input
provides ±16.5V fault protection for the bipolar input
devices and ±6.0V fault protection for the unipolar input
device. This fault protection circuit limits the current going
into or out of the device to less than 50mA, providing an
added layer of protection from momentary overvoltage or
undervoltage conditions at the analog input.
Power-Saving Modes
Shutdown Mode
During shutdown, the analog and digital circuits in the
device power down and the device draws less than
100µA from AV
DD
, and less than 100µA from DV
DD
.
Select shutdown mode using the SHDN input. Set
SHDN high to enter shutdown mode. After coming out
of shutdown, allow the 1ms wake-up before making the
first conversion. When using an external clock, apply at
least 20 clock cycles with CONVST high before making
the first conversion. When using internal clock mode,
wait at least 2µs before making the first conversion.
Clock Modes
These devices provide an internal clock of 10MHz
(typ). Alternatively, an external clock can be used.
Internal Clock
Internal clock mode frees the microprocessor from the
burden of running the ADC conversion clock. For inter-
nal clock operation, connect INTCLK/EXTCLK to AV
DD
and connect CLK to DGND.
External Clock
For external clock operation, connect INTCLK/EXTCLK
to AGND and connect an external clock source to CLK.
Note that INTCLK/EXTCLK is referenced to the analog
power supply, AV
DD
. The external clock frequency can
be up to 15MHz, with a duty cycle between 30% and
70%. Clock frequencies of 100kHz and lower can be
used, but the droop in the T/H circuits reduces linearity.
Selecting an Input Buffer
Most applications require an input buffer to achieve 14-
bit accuracy. Although slew rate and bandwidth are
important, the most critical specification is settling time.
The sampling requires a relatively brief sampling inter-
val of 150ns. At the beginning of the acquisition, the
internal sampling capacitor array connects to the
amplifier output, causing some output disturbance.
Ensure the amplifier is capable of settling to at least 14-
bit accuracy during this interval. Use a low-noise, low-
distortion, wideband amplifier (such as the MAX4330 or
MAX4265), which settles quickly and is stable with the
ADC’s capacitive load (in parallel with any bypass
capacitors on the analog inputs).
Figure 2. Typical Input Circuit
