MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
16 ______________________________________________________________________________________
Unipolar 0 to +5V Device
Table 4 and Figure 8 show the offset binary transfer func-
tion for the MAX1319 with a 0 to +5V input range. The
FSR is two times the voltage at REF. The internal +2.500V
reference gives a +5V FSR, while an external +2V to +3V
reference allows an FSR of +4V to +6V, respectively.
Calculate the LSB size using the following equation:
This equals 0.3052mV when using the internal reference.
The input range is centered about V
MSV
, which is inter-
nally set to +2.500V. For a custom midscale voltage,
drive REF
MS
with an external voltage source and MSV
will follow REF
MS
. Noise present on MSV or REF
MS
directly couples into the ADC result. Use a precision,
low-drift voltage reference with adequate bypassing to
prevent MSV from degrading ADC performance. For
maximum full-scale range, be careful not to violate the
absolute maximum voltage ratings of the analog inputs
when choosing MSV. Determine the input voltage as a
function of V
REF
, V
MSV
, and the output code in decimal
using the following equation:
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. For these
devices this straight line is a line drawn between the
endpoints of the transfer function, once offset and gain
errors have been nullified.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. For
these devices, the DNL of each digital output code is
measured and the worst-case value is reported in the
Electrical Characteristics table. A DNL error specifica-
tion of less than ±1 LSB guarantees no missing codes
and a monotonic transfer function.
Unipolar Offset Error
For the unipolar MAX1319, the ideal midscale transition
from 0x1FFF to 0x2000 occurs at MSV (see Figure 8).
The unipolar offset error is the amount of deviation
between the measured midscale transition point and
the ideal midscale transition point.
V LSB CODE V
CH MSV_
+
()
10
- 2.500V
1
2
2
14
LSB
V
REFADC
=
×
Table 4. 0 to +5V Unipolar Code Table
BINARY OUTPUT CODE
DECIMAL
EQUIVALENT
OUTPUT
(CODE
10
)
INPUT
VOLTAGE (V)
(V
REF
= V
REFMS
= 2.5V)
11 1111 1111 1111
0x3FFF
16383 4.9997
11 1111 1111 1110
0x3FFE
16382 4.9994
10 0000 0000 0001
0x2001
8193 2.5003
10 0000 0000 0000
0x2000
8192 2.5000
01 1111 1111 1111
0x1FFF
8191 2.4997
00 0000 0000 0001
0x0001
1 0.0003
00 0000 0000 0000
0x0000
00
Figure 8. 0 to +5V Unipolar Transfer Function
2 x V
REFADC
2 x V
REFADC
2 x V
REFADC
2
14
1 LSB =
BINARY OUTPUT CODE
0 2 16,38316,381
0x0000
0x0001
0x0002
0x0003
0x3FFF
0x3FFE
0x3FFD
0x3FFC
0x1FFF
0x2000
0x2001
8190
8192
8194
(MSV)
INPUT VOLTAGE (LSBs)
MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
______________________________________________________________________________________ 17
Bipolar Offset Error
For the bipolar MAX1323/MAX1327, the ideal zero-point
transition from 0x3FFF to 0x0000 occurs at MSV, which
is usually connected to ground (see Figures 6 and 7).
The bipolar offset error is the amount of deviation
between the measured zero-point transition and the
ideal zero-point transition.
Gain Error
The ideal full-scale transition from 0x1FFE to 0x1FFF
occurs at 1 LSB below full scale (see the Transfer
Functions section). The gain error is the amount of devi-
ation between the measured full-scale transition point
and the ideal full-scale transition point, once offset error
has been nullified.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s res-
olution (N bits):
where N = 14 bits.
In reality, there are other noise sources besides quanti-
zation noise; thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the ENOB as follows:
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V
1
is the fundamental amplitude and V
2
through
V
5
are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component.
Aperature Delay
Aperture delay (t
AD
) is the time delay from the sampling
clock edge to the instant when an actual sample is taken.
Aperture Jitter
Aperture Jitter (t
AJ
) is the sample-to-sample variation in
aperture delay.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in a manner that ensures that the signal’s slew
rate does not limit the ADC’s performance. The input
frequency is then swept up to the point where the
amplitude of the digitized conversion result has
decreased by -3dB.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
THD
VVVV
V
+++
20
2
2
3
2
4
2
5
2
1
log
ENOB
SINAD
=
-176
602
.
.
SINAD dB
Signal
Noise Distortion
RMS
RMS
( ) log
()
+
20
SNR N dB+(. . )602 176
Chip Information
TRANSISTOR COUNT: 80,000
PROCESS: 0.6µm BiCMOS
MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
18 ______________________________________________________________________________________
Typical Operating Circuits
MAX1319
CH0
I.C.
I.C.
I.C.
I.C.
I.C.
I.C.
I.C.
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
AV
DD
AGND
DV
DD
DGND
MSV
REF
MS
REF
REF+
COM
REF-
+5V
GND
+3V
GND
D13
SHDN
ALLON
ANALOG
INPUTS
0 TO +5V
PARALLEL
DIGITAL
OUTPUTS
CONVST
CLK
DIGITAL
INTERFACE
AND
CONTROL
4
5
7
8
9
10
11
12
2, 3, 14, 16, 23
21
22
20
19
18
6
17
44
42
38
45
47
48
46
40
41
37
36
35
34
33
32
31
30
29
28
27
26
25
24
39
13
AV
DD
AV
DD
15
1
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.01µF
0.1µF
0.01µF
2.2µF
2.2µF
2.2µF
UNIPOLAR
CONFIGURATION
INTCLK/EXTCLK
CS
RD
EOC
EOLC
I.C.2

MAX1319ECM+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
IC ADC 14BIT 526KSPS 48LQFP
Lifecycle:
New from this manufacturer.
Delivery:
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