MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
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Pin Description (continued)
PIN NAME FUNCTION
22 REF-
N eg ati ve Refer ence Byp ass. RE F- i s the b yp ass p oi nt for an i nter nal l y g ener ated r efer ence vol tag e. Byp ass
RE F- w i th a 0.1µF cap aci tor to AG N D . Al so b yp ass RE F- to RE F+ w i th a 2.2µF and a 0.1µF cap aci tor .
24 D0 Digital Out Bit 0 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
25 D1 Digital Out Bit 1 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
26 D2 Digital Out Bit 2 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
27 D3 Digital Out Bit 3 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
28 D4 Digital Out Bit 4 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
29 D5 Digital Out Bit 5 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
30 D6 Digital Out Bit 6 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
31 D7 Digital Out Bit 7 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
32 D8 Digital Out Bit 8 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
33 D9 Digital Out Bit 9 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
34 D10 Digital Out Bit 10 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
35 D11 Digital Out Bit 11 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
36 D12 Digital Out Bit 12 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
37 D13 Digital Out Bit 13 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
38 DV
DD
Digital Supply Input. Apply +2.7V to +5.25V to DV
DD
. Bypass DV
DD
to DGND with a 0.1µF capacitor.
39 DGND
Digital Supply GND. DGND is the power return for DV
DD
. Connect DGND to AGND at only one point
(see the Layout, Grounding, and Bypassing section).
40 EOC
End-of-Conversion Output. EOC goes low to indicate the end of a conversion. EOC returns high after
one clock period.
41 EOLC
End-of-Last-Conversion Output. EOLC goes low to indicate the end of the last conversion. EOLC
returns high when CONVST goes low for the next conversion sequence. For the MAX1319/MAX1323/
MAX1327, EOLC gives the same information as EOC.
42 RD
Read Input. Pulling RD low initiates a read command of the parallel data buses, D0–D13. D0–D13 are
high impedance while either RD or CS is high.
43 I.C.2 Internally Connected 2. Connect I.C.2 to DV
DD
.
44 CS
Chip-Select Input. Pulling CS low activates the digital interface. D0–D13 are high impedance while
either CS or RD is high.
45 CONVST
Convert-Start Input. Driving CONVST high places the device in hold mode and initiates the
conversion process. The analog inputs are sampled on the rising edge of CONVST. When CONVST
is low the analog inputs are tracked.
46 CLK
External-Clock Input. CLK accepts an external clock signal up to 15MHz. Connect CLK to DGND for
internally clocked conversions. To select external clock mode, set INTCLK/EXTCLK = 0.
47 SHDN Shutdown Input. Set SHDN = 0 for normal operation. Set SHDN = 1 for shutdown mode.
48 ALLON ALLON is not implemented. Connect ALLON to DGND.
