9397 750 13429 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 06 — 2 August 2004 2 of 13
Philips Semiconductors
PHB/PHD66NQ03LT
N-channel TrenchMOS™ logic level FET
3. Ordering information
4. Limiting values
Table 2: Ordering information
Type number Package
Name Description Version
PHB66NQ03LT D
2
-PAK Plastic single-ended surface mounted package (Philips version of D
2
-PAK);
3 leads (one lead cropped)
SOT404
PHD66NQ03LT D-PAK Plastic single-ended surface mounted package (Philips version of D-PAK);
3 leads (one lead cropped)
SOT428
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
drain-source voltage (DC) 25 °C ≤ T
j
≤ 175 °C - 25 V
V
DGR
drain-gate voltage (DC) 25 °C ≤ T
j
≤ 175 °C; R
GS
=20kΩ -25V
V
GS
gate-source voltage (DC) - ±20 V
I
D
drain current (DC) T
mb
=25°C; V
GS
=5V;Figure 2 and 3 -57A
T
mb
= 100 °C; V
GS
=5V;Figure 2 -40A
T
mb
=25°C; V
GS
=10V - 66 A
T
mb
= 100 °C; V
GS
=10V - 45 A
I
DM
peak drain current T
mb
=25°C; pulsed; t
p
≤ 10 µs; Figure 3 - 228 A
P
tot
total power dissipation T
mb
=25°C; Figure 1 -93W
T
stg
storage temperature −55 +175 °C
T
j
junction temperature −55 +175 °C
Source-drain diode
I
S
source (diode forward) current (DC) T
mb
=25°C - 57 A
I
SM
peak source (diode forward) current T
mb
=25°C; pulsed; t
p
≤ 10 µs - 228 A
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source
avalanche energy
unclamped inductive load; I
D
=43A;
t
p
= 0.15 ms; V
DD
≤ 25 V; R
GS
=50Ω;
V
GS
= 10 V; starting at T
j
=25°C
-90mJ
