Dual Ultrafast
Voltage Comparator
ADCMP565
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
FEATURES
300 ps propagation delay input to output
50 ps propagation delay dispersion
Differential ECL compatible outputs
Differential latch control
Robust input protection
Input common-mode range −2.0 V to +3.0 V
Input differential range ±5 V
Power supply sensitivity greater than 65 dB
200 ps minimum pulsewidth
5 GHz equivalent input rise time bandwidth
Typical output rise/fall of 160 ps
SPT 9689 replacement
APPLICATIONS
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers and signal restoration
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Clock drivers
Automatic test equipment
FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
INPUT
INVERTING
INPUT
LATCH ENABLE
INPUT
Q OUTPUT
Q OUTPUT
LATCH ENABLE
INPUT
02820-0-001
ADCMP565
Figure 1.
GENERAL DESCRIPTION
The ADCMP565 is an ultrafast voltage comparator fabricated
on Analog Devices proprietary XFCB process. The device
features 300 ps propagation delay with less than 50 ps overdrive
dispersion. Overdrive dispersion, a particularly important
characteristic of high speed comparators, is a measure of the
difference in propagation delay under differing overdrive
conditions.
A fast, high precision differential input stage permits consis-
tent propagation delay with a wide variety of signals in the
common-mode range from −2.0 V to +3.0 V. Outputs are
complementary digital signals fully compatible with ECL 10 K
and 10 KH logic families. The outputs provide sufficient drive
current to directly drive transmission lines terminated in 50 Ω
to −2 V. A latch input is included, which permits tracking,
track-and-hold, or sample-and-hold modes of operation.
The ADCMP565 is available in a 20-lead PLCC package.
ADCMP565* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
EVALUATION KITS
ADCMP565 Evaluation Board
DOCUMENTATION
Data Sheet
ADCMP565: 20L-PLCC Ultra Fast High Speed Comparator
ECL Compatible Data Sheet
DESIGN RESOURCES
ADCMP565 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all ADCMP565 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
ADCMP565
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Considerations.............................................................. 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Timing Information ......................................................................... 8
Application Information.................................................................. 9
Clock Timing Recovery ............................................................... 9
Optimizing High Speed Performance ........................................9
Comparator Propagation Delay Dispersion ..............................9
Comparator Hysteresis .............................................................. 10
Minimum Input Slew Rate Requirement................................ 10
Typical Application Circuits ..................................................... 11
Typical Performance Characteristics ........................................... 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
Revision 0: Initial Version

ADCMP565BP

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Comparators DUAL CHANNEL HIGH SPEED COMPARATOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet