OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADCMP565BP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
ADCMP565
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
3 2 1 20 19
910111213
18
17
16
15
14
4
5
6
7
8
PIN 1
IDENTIFIER
NC = NO CONNECT
G
ND
LEA
NC
V
EE
GND
LEB
NC
V
CC
ADCMP565
TOP VIEW
(Not to Scale)
QA
NC
QB
–INA
+INA
NC
+INB
–INB
QA
LEA LEB
QB
02820-0-002
Figure 2. ADCMP565 Pin Configuration
Table 3. ADCMP565 Pin Descriptions
Pin No. Mnemonic Function
1 NC No Connect. Leave pin unconnected.
2 QA
One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 5) for more information.
3
QA
One of two complementary outputs for Channel A.
QA
will be at logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEA description (Pin 5) for more information.
4 GND Analog Ground
5 LEA
One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode.
LEA
must be driven
in conjunction with LEA.
6 NC No Connect. Leave pin unconnected or attach to GND (internally connected to GND).
7
LEA
One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the
output will track changes at the input of the comparator. In the latch mode (logic high), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven
in conjunction with
LEA
.
8 V
EE
Negative Supply Terminal
9 −INA
Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven
in conjunction with the noninverting A input.
10 +INA
Noninverting analog input of the differential input stage for Channel A. The noninverting A input must
be driven in conjunction with the inverting A input.
11 NC No Connect. Leave pin unconnected.
12 +INB
Noninverting analog input of the differential input stage for Channel B. The noninverting B input must
be driven in conjunction with the inverting B input.
13 −INB
Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven
in conjunction with the noninverting B input.
14 V
CC
Positive Supply Terminal
15
LEB
One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the
output will track changes at the input of the comparator. In the latch mode (logic high), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven
in conjunction with
LEB
.
16 NC No Connect. Leave pin unconnected or attach to GND (internally connected to GND).
17 LEB
One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode.
LEB
must be driven
in conjunction with LEB.
ADCMP565
Rev. 0 | Page 7 of 16
Pin No. Mnemonic Function
18 GND Analog Ground
19
QB
One of two complementary outputs for Channel B.
QB
will be at logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEB description (Pin 17) for more information.
20 QB
One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEB description (Pin 17) for more information.
ADCMP565
Rev. 0 | Page 8 of 16
TIMING INFORMATION
50%
50%
V
REF
± V
OS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
Q OUTPUT
LATCH ENABLE
t
H
t
PDL
t
PDH
t
PLOH
t
PLOL
t
R
t
F
V
IN
V
OD
t
S
t
PL
02820-0-003
Figure 3. System Timing Diagram
The timing diagram in Figure 3 shows the ADCMP565 compare
and latch features. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol Timing Description
t
PDH
Input to output
high delay
Propagation delay measured from
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output low-to-high transition
t
PDL
Input to output
low delay
Propagation delay measured from
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output high-to-low transition
t
PLOH
Latch enable
to output high
delay
Propagation delay measured from
the 50% point of the Latch Enable
signal low-to-high transition to
the 50% point of an output low-
to-high transition
t
PLOL
Latch enable
to output low
delay
Propagation delay measured from
the 50% point of the Latch Enable
signal low-to-high transition to
the 50% point of an output high-
to-low transition
Symbol Timing Description
t
H
Minimum
hold time
Minimum time after the negative
transition of the Latch Enable
signal that the input signal must
remain unchanged to be acquired
and held at the outputs
t
PL
Minimum
latch enable
pulse width
Minimum time that the Latch
Enable signal must be high to
acquire an input signal change
t
S
Minimum
setup time
Minimum time before the
negative transition of the Latch
Enable signal that an input signal
change must be present to be
acquired and held at the outputs
t
R
Output rise
time
Amount of time required to
transition from a low to a high
output as measured at the 20%
and 80% points
t
F
Output fall
time
Amount of time required to
transition from a high to a low
output as measured at the 20%
and 80% points
V
OD
Voltage
overdrive
Difference between the
differential input and reference
input voltages
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ADCMP565BP

Mfr. #:
Buy ADCMP565BP
Manufacturer:
Analog Devices Inc.
Description:
Analog Comparators DUAL CHANNEL HIGH SPEED COMPARATOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet