NCV70522DQ
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21
READ Operation
If the Master wants to read data from Status or Control
Registers, it initiates the communication by sending a
READ command. This READ command contains the
address of the SPI register to be read out. At the falling edge
of the eighth clock pulse the data−out shift register is
updated with the content of the corresponding internal SPI
register. In the next 8−bit clock pulse train this data is shifted
out via DO pin. At the same time the data shifted in from DI
(Master) should be interpreted as the following successive
command or dummy data.
Figure 18. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master
DATA from previous command or
NOT VALID after POR or RESET
Registers are updated with the internal status at the rising edge
of the internal NCV70522DQ clock when CS
= 1
READ DATA from ADDR1 COMMAND or DUMMY
OLD DATA or NOT VALID DATA from ADDR1
COMMAND
DATA DATA
DO
DI
CS
All 4 Status Registers (see SPI Registers) contain 7 data
bits and an even parity check bit. The most significant bit
(D7) represents a parity of D[6:0]. If the number of logical
ones in D[6:0] is odd, the parity bit D7 equals “1”. If the
number of logical ones in D[6:0] is even then the parity bit
D7 equals “0”. This simple mechanism protects against
noise and increases the consistency of the transmitted data.
If a parity check error occurs it is recommended to initiate
an additional READ command to obtain the status again.
Also the Control Registers can be read out following the
same routine. Control Registers don’t have a parity check.
The CS
line is active low and may remain low between
successive READ commands as illustrated in Figure 20.
There is however one exception. In case an error condition
is latched in one of Status Registers (see SPI Registers) the
ERR
pin is activated. (See the “Error Output” Section). This
signal flags a problem to the external microcontroller. By
reading the Status Registers information, the root cause of
the problem can be determined. After this READ operation
the Status Registers are cleared. Because the Status
Registers and ERR
pin (see SPI Registers) are only updated
by the internal system clock when the CS
line is high, the
Master should force CS
high immediately after the READ
operation. For the same reason it is recommended to keep
the CS
line high always when the SPI bus is idle.
WRITE Operation
If the Master wants to write data to a Control Register it
initiates the communication by sending a WRITE
command. This contains the address of the SPI register to
write to. The command is followed with a data byte. This
incoming data will be stored in the corresponding Control
Register after CS
goes from low to high! NCV70522DQ
responds on every incoming byte by shifting out via DO the
data stored in the last received address.
It is important that the writing action (command − address
and data) to the Control Register is exactly 16 bits long. If
more or less bits are transmitted the complete transfer packet
is ignored.
A WRITE command executed for a read−only register
(e.g. Status Registers) will not affect the addressed register
and the device operation.
Because after a power−on−reset the initial address is
unknown the data shifted out via DO is not valid.
DATA from previous command or
NOT VALID after POR or RESET
DO
DI
CS
WRITE DATA to ADDR3 NEW DATA for ADDR3
OLD DATA or NOT VALID
OLD DATA from ADDR3
COMMAND
DATA DATA
DATA
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
Figure 19. Single WRITE Operation where DATA from the Master is Written in SPI Register with Address 3
