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NCV70522DQ004G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
NCV70522DQ
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7
Table 6. AC PARAMETERS (The AC Parameters are Given for V
BB
and Temperature in Their Operating Ranges)
Symbol
Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit
INTERNAL OSCILLATOR
f
osc
Frequency of Internal Oscillator 3.6 4.0 4.4 MHz
MOTORDRIVER
f
PWM
MOTxx
PWM Frequency
Frequency Depends Only on
Internal Oscillator
20.8 22.8 24.8 kHz
Double PWM Frequency 41.6 45.6 49.6 kHz
f
d
PWM Jitter Depth (Note 13) 10 % f
PWM
tb
rise
MOTxx
Turn−On Voltage Slope, 10% to 90%
(Note 13)
EMC[1:0] = 00 150
V/ms
EMC[1:0] = 01 100
V/ms
EMC[1:0] = 10 50
V/ms
tb
fall
MOTxx
Turn−off Voltage Slope, 90% to 10%
(Note 13)
EMC[1:0] = 00 150
V/ms
EMC[1:0] = 01 100
V/ms
EMC[1:0] = 10 50
V/ms
DIGITAL OUTPUTS
t
H2L
DO
ERR
Output Falltime from V
inH
to V
inL
Capacitive Load 400 pF and
Pullup Resistor of 1.5 kW
50 ns
CHARGE PUMP
f
CP
CPN
CPP
Charge Pump Frequency 250 kHz
t
CPU
MOTxx Startup Time of Charge Pump (Note 14) Spec External Components 5.0 ms
CLR FUNCTION
t
CLR
CLR Minimum Time for Hard Reset 100
ms
NXT FUNCTION
t
NXT_HI
NXT
NXT Minimum, High Pulse Width See Figure 3 2.0
ms
t
NXT_LO
NXT Minimum, Low Pulse Width See Figure 3 2.0
ms
t
DIR_SET
NXT Hold Time, Following
Change of DIR
See Figure 3 2.0
ms
t
DIR_HOLD
NXT Hold Time, Before Change of DIR See Figure 3 2.0
ms
POWER UP
t
PU
PORB
/
WD
Power−Up Time
V
BB
= 12 V, I
LOAD
= 50 mA,
C
LOAD
= 220 nF
110
ms
t
POR
Reset Duration 100 ms
t
RF
Reset Filter Time 1.0
ms
WATCHDOG
t
WDTO
Watchdog Time Out Interval 32 512 ms
t
WDPR
Prohibited Watchdog
Acknowledge Delay
2.0 ms
13.Characterization Data Only
14.Guaranteed by design.
NCV70522DQ
www.onsemi.com
8
DIR
NXT
VALID
Figure 3. NXT−Input Timing Diagram
t
DIR_SET
t
DIR_HOLD
0.5 V
CC
t
NXT_HI
t
NXT_LO
Table 7. SPI TIMING PARAMETERS
Symbol Parameter Min Typ Max Unit
t
CLK
SPI Clock Period 1
ms
t
CLK_HIGH
SPI Clock High Time 100 ns
t
CLK_LOW
SPI Clock Low Time 100 ns
t
SET_DI
DI Setup Time, Valid Data Before Rising Edge of CLK 50 ns
t
HOLD_DI
DI Hold Time, Hold Data After Rising Edge of CLK 50 ns
t
CSB_HIGH
CS High Time 2.5
ms
t
SET_CSB
CS Setup Time, CS Low Before Rising Edge of CLK 100 ns
t
SET_CLK
CLK Setup Time, CLK Low Before Rising Edge of CS 100 ns
DI
VALID
CLK
Figure 4. SPI Timing
CS
0.8 V
CC
0.2 V
CC
0.2 V
CC
0.2 V
CC
0.2 V
CC
0.8 V
CC
t
CLK
t
SET_CLK
t
SET_CSB
t
SET_DI
t
CLK_HI
t
CLK_LO
t
HOLD_DI
NCV70522DQ
www.onsemi.com
9
TYPICAL APPLICATION SCHEMATIC
DIR
NXT
DO
DI
CLK
CLR
SLA
100 nF
100 nF 100 nF 100 nF
VDD
VBB
VCP
CPN
CPP
MOTXP
MOTXN
MOTYP
MOTYN
220 nF
R
3
R
2
C
4
C
2
C
3
C
6
C
7
M
C
5
TSTO
GND
C
8
R
1
+
C
1
CS
ERR
Figure 5. Typical Application Schematic NCV70522DQ
NCV70522DQ
mC
220 nF
100 mF
V
BAT
POR/WD
R
4
D
1
VBB
Table 8. EXTERNAL COMPONENTS LIST AND DESCRIPTION
Component Function Typ. Value Tolerance Unit
C
1
V
BB
Buffer Capacitor (Low ESR < 1 W)
100 −20 +80%
mF
C
2
, C
3
V
BB
Decoupling Block Capacitor 100 −20 +80% nF
C
4
V
DD
Buffer Capacitor 220 $20% nF
C
5
V
DD
Buffer Capacitor 100 $20% nF
C
6
Charge−Pump Buffer Capacitor 220 $20% nF
C
7
Charge−Pump Pumping Capacitor 220 $20% nF
C
8
Low Pass Filter SLA 1 $20% nF
R
1
Low Pass Filter SLA 5.6 $1%
kW
R
2
, R
3
Pullup Resistor Open Drain Output 4.7 $1%
kW
D
1
Reverse Protection Diode MURD530
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

NCV70522DQ004G

Mfr. #:
Buy NCV70522DQ004G
Manufacturer:
ON Semiconductor
Description:
Motor / Motion / Ignition Controllers & Drivers SPI STEPPER DVR VREG
Lifecycle:
New from this manufacturer.
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