NCV70522DQ
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22
Examples of Combined READ and WRITE Operations
In the following examples successive READ and WRITE
operations are combined. In Figure 20 the Master first reads
the status from Register at ADDR4 and at ADDR5 followed
by writing a control byte in Control Register at ADDR2.
Note that during the write command (in Figures 19 and 20)
the old data of the pointed register is returned at the moment
the new data is shifted in.
Figure 20. Two Successive READ Commands Followed by a WRITE Command
COMMAND
COMMAND COMMAND
DATA
DATA
DATA DATA
DATA
DO
DI
CS
DATA from previous
command or NOT VALID
after POR or RESET
READ DATA
from ADDR4
READ DATA
from ADDR5
WRITE DATA
to ADDR2
NEW DATA
for ADDR2
OLD DATA
or NOT VALID
DATA
from ADDR4
DATA
from ADDR5
OLD DATA
from ADDR2
Registers are updated with the internal status at the rising
edge of the internal NCV70522DQ clock when CS = 1
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
After the write operation the Master could initiate a read
back command in order to verify if the data is correctly
written, as illustrated in Figure 21. During reception of the
READ command the old data is returned for a second time.
Only after receiving the READ command the new data is
transmitted. This rule also applies when the master device
wants to initiate an SPI transfer to read the Status Registers.
Because the internal system clock updates the Status
Registers only when CS
line is high, the first read out byte
might represent old status information.
COMMAND
DATA DATA DATA DATA
OLD DATA
or NOT VALID
OLD DATA
from ADDR2
OLD DATA
from ADDR2
NEW DATA
from ADDR2
DO
DI
CS
Figure 21. A WRITE Operation where DATA from the Master is Written in SPI Register with Address 2 Followed by
a READ Back Operation to Verify a Correct WRITE Operation
DATA COMMAND
WRITE DATA
to ADDR2
NEW DATA
for ADDR2
READ DATA
from ADDR2
COMMAND or
DUMMY
Registers are Updated with the Internal
Status at the Rising Edge of CS
Registers are Updated with the In-
ternal Status at the Rising Edge of
the Internal NCV70522DQ Clock
when CS
= 1
DATA from previous
command or NOT VALID
after POR or RESET
NOTE: The internal data−out shift buffer of the NCV70522DQ is updated with the content of the selected SPI register only at the last (every
eighth) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be
written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
Table 11. SPI CONTROL REGISTERS
(All SPI Control Registers have Read/Write Access and default to “0” after Power−on or hard reset)
Address
Content
Structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
CRWD (00h) Data WDEN WDT[3:0] 0 0 0
CR0 (01h) Data SM[2:0] CUR[4:0]
CR1 (02h) Data DIRCTRL NXTP − − PWMF PWMJ EMC[1:0]
CR2 (03h) Data MOTEN SLP SLAG SLAT − − − −
Where:
R/W: Read and Write access
Reset: Status after Power−On or hard reset
WDEN: Watchdog enable. Writing “0” to this bit will clear WD bit (see SPI Status Register 0)
WDT[3:0]: Watchdog timeout interval
