NCV70522DQ
www.onsemi.com
5
Table 5. DC PARAMETERS
(The DC Parameters are Given for V
BB
and Temperature in Their Operating Ranges Unless Otherwise Specified)
Convention: Currents Flowing in the Circuit are Defined as Positive.
Symbol
Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit
SUPPLY INPUTS
V
BB
V
BB
Nominal Operating Supply Range 6 30 V
I
BB
Total Current Consumption Unloaded Outputs 12 mA
I
BBS
Sleep Current in V
BB
(Note 7) Unloaded Outputs 400
mA
V
DD
V
DD
Logic Supply Output Voltage 4.5 5 5.5 V
I
Load
Maximum Output Current
6 V ≤ V
BB
≤ 8 V 15 mA
8 V ≤ V
BB
≤ 30 V 40 mA
I
DDLIM
Current Limitation 150 mA
I
Load_PD
Output Current in Power Down Mode 1 mA
POWER ON RESET (POR) (Note 10)
V
DDH
V
DD
Internal POR Comparator Threshold V
DD
Rising 3.6 4.20 4.5 V
V
DDL
Internal POR Comparator Threshold V
DD
Falling 3.85 V
V
DDHYS
Hysteresis Between V
DDH
and V
DDL
0.10 0.35 0.60 V
MOTOR DRIVER
I
MDmax,Peak
MOTXP
MOTXN
MOTYP
MOTYN
Max Peak Current Through Motor Coil T
J
= 125°C 1480 mA
I
MDmax,Peak
Max Peak Current Through Motor Coil T
J
= −40°C 1600 mA
I
MDabs
Absolute Error on Coil Current
T
J
= 125°C and
CUR[4:0] = 15...31
−10 10 %
I
MDrel
Error On Current Ratio I
coilx
/I
coily
−7 7 %
I
SET_TC1
Temperature Coefficient of Coil Current
Set−Level, CUR[4:0] = 0...27
T
J
≤ 160°C −240 ppm/K
I
SET_TC2
Temperature Coefficient of Coil Current
Set−Level, CUR[4:0] = 28...31
T
J
≤ 160°C −490 ppm/K
R
HS
On−Resistance High−Side Driver,
(Note 9) CUR[4:0] = 0...31
V
BB
= 12 V, T
J
= 27°C 0.45
W
V
BB
= 12 V, T
J
= 160°C 0.94 1.25
W
R
LS3
On−Resistance Low−Side Driver,
(Note 9) CUR[4:0] = 23...31
V
BB
= 12 V, T
J
= 27°C 0.45
W
V
BB
= 12 V, T
J
= 160°C 0.94 1.25
W
R
LS2
On−Resistance Low−Side Driver,
(Note 9) CUR[4:0] = 16...22
V
BB
= 12 V, T
J
= 27°C 0.90
W
V
BB
= 12 V, T
J
= 160°C 1.9 2.5
W
R
LS1
On−Resistance Low−Side Driver,
(Note 9) CUR[4:0] = 9...15
V
BB
= 12 V, T
J
= 27°C 1.8
W
V
BB
= 12 V, T
J
= 160°C 3.8 5.0
W
R
LS0
On−Resistance Low−Side Driver,
(Note 9) CUR[4:0] = 0...8
V
BB
= 12 V, T
J
= 27°C 3.6
W
V
BB
= 12 V, T
J
= 160°C 7.5 10
W
I
Mpd
Pulldown Current HiZ Mode 1 mA
DIGITAL INPUTS
I
leak
DI, CLK
NXT, DIR
CLR, CS
Input Leakage (Note 8) T
J
= 160°C 0.5
mA
V
IL
Logic Low Threshold Tested at 1 MHz frequency 0 0.6 V
V
IH
Logic High Threshold Tested at 1 MHz frequency 2.4 V
DD
V
R
pd_CLR
CLR Internal Pulldown Resistor 120 300
kW
R
pd_TST
TST0 Internal Pulldown Resistor 3 9
kW
6. Current with oscillator running, all analogue cells active, SPI communication and NXT pulses applied. No floating inputs. Guaranteed by
design.
7. Current with all analogue cells in power down. Logic is powered but no clocks running. All outputs unloaded, no inputs floating.
8. Not valid for pins with internal Pulldown resistor
9. Characterization Data Only
10.POR is derived from V
DD
. For proper POR operation V
BB
needs to be minimal V
BB_min
.
