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AD974BR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
REV. A
AD974
–12–
EXTERNAL CONTINUOUS CLOCK DATA READ DURING
CONVERSION WITH SYNC OUTPUT GENERATED
Figure 9 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a continu-
ous external clock with the generation of a SYNC output. What
permits the generation of a SYNC output is a transition of
DATACLK either while CS is high or while both CS and R/C
are low.
With a continuous clock the CS pin cannot be tied low as it
could be with a discontinuous clock. Use of a continuous clock
while a conversion is occurring can increase the DNL and
Transition Noise.
In Figure 9 a conversion is initiated by taking R/C low with CS
held low. While this condition exists a transition of DATACLK,
clock pulse #0, will enable the generation of a SYNC pulse. Less
then 83 ns after R/C is taken low the BUSY output will go low
to indicate that the conversion process has began. Figure 9
shows R/C then going high and after a delay of greater than
15 ns (t
15
), clock pulse #1 can be taken high to request the
SYNC output. The SYNC output will appear approximately
50 ns after this rising edge and will be valid on the falling edge
of clock pulse #1 and the rising edge of clock pulse #2. The
MSB will be valid approximately 40 ns after the rising edge of
clock pulse #2 and can be latched off either the falling edge of
clock pulse #2 or the rising edge of clock pulse #3. The LSB
will be valid on the falling edge of clock pulse #17 and the
rising edge of clock pulse #18.
Data should be clocked out during the 1st half of BUSY to
not degrade conversion performance. This requires use of a
10 MHz DATACLK or greater, with data being read out as
soon as the conversion process begins.
t
12
t
13
t
14
EXT
DATACLK
CS
R/C
BUSY
SYNC
DATA
t
16
t
15
t
19
t
1
t
20
t
2
t
17
t
12
t
18
t
18
BIT 15
(MSB)
BIT 0
(LSB)
0123 18
Figure 9. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion
Using An External Continuous Data Clock (EXT/
INT
Set to Logic High)
REV. A
AD974
–13–
Table I. Analog Input Configuration
Input Voltage Connect Connect Input
Range VxA to VxB to Impedance
±10 V BIP V
IN
13.7 kΩ
0 V to +5 V V
IN
GND 6.0 kΩ
0 V to +4 V V
IN
V
IN
6.4 kΩ
Table II. Output Codes and Ideal Input Voltage
Digital Input
Description Analog Input Straight Binary
Full-Scale Range ±10 V 0 V to +5 V 0 V to +4 V
Least Significant Bit 305 µV 76 µV 61 µV
+Full Scale (FS – 1 LSB) +9.999695 V +4.999847 V +3.999939 V 1111 1111 1111 1111
Midscale 0 V +2.5 V +2 V 1000 0000 0000 0000
One LSB Below Midscale –305 µV +2.499924 V +1.999939 V 0111 1111 1111 1111
–Full Scale –10 V 0 V 0 V 0000 0000 0000 0000
ANALOG INPUTS
The AD974 is specified to operate with three full-scale analog
input ranges. Connections required for each of the eight analog
inputs, VxA and VxB and the resulting full-scale ranges, are
shown in Table I. The nominal input impedance for each ana-
log input range is also shown. Table II shows the output codes
for the ideal input voltages of each of the analog input ranges.
The analog input section has a ±25␣ V overvoltage protection on
VxA and VxB. Since the AD974 has two analog grounds it is
important to ensure that the analog input is referenced to the
AGND1 pin, the low current ground. This will minimize any
problems associated with a resistive ground drop. It is also
important to ensure that the analog inputs are driven by a low
impedance source. With its primarily resistive analog input
circuitry, the ADC can be driven by a wide selection of general
purpose amplifiers.
To achieve the low distortion capability of the AD974 care
should be taken in the selection of the drive circuitry
op amp.
Figure 10 shows the simplified analog input section for the
AD974. Since the AD974 can operate with an internal or exter-
nal reference, and three different analog input ranges, the full-
scale analog input range is best represented with a voltage that
spans 0␣ V to V
REF
across the 40 pF sampling capacitor. The on-
chip resistors are laser trimmed to ratio match for adjustment of
offset and full-scale error using fixed external resistors.
BIP AGND1 REF
CAP
VxA
VxB
AGND2
3kV
12kV
4kV
SWITCHED
CAP ADC
2.5V
REFERENCE
4kV
40pF
AD974
Figure 10. Simplified Analog Input
REV. A
AD974
–14–
BIP
VxA
VxB
AGND1
CAP
REF
AGND2
AD974
V
IN
2.2mF
2.2mF
+
+
BIP
VxA
VxB
AGND1
CAP
REF
AGND2
AD974
V
IN
2.2mF
2.2mF
+
+
BIP
VxA
VxB
AGND1
CAP
REF
AGND2
AD974
V
IN
2.2mF
2.2mF
+
+
INPUT RANGE BASIC CONNECTIONS FOR AD974
610V
0V TO +5V
0V TO +4V
Figure 11. Analog Input Configurations
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD974BR

Mfr. #:
Buy AD974BR
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 4CH 16-Bit 200 kSPS
Lifecycle:
New from this manufacturer.
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