REV. A
AD974
–8–
can be read after the conversion is complete. The external clock
can be either a continuous or discontinuous clock. A discontinu-
ous clock can be either normally low or normally high when
inactive. In the case of the discontinuous clock, the AD974 can be
configured to either generate or not generate a SYNC output
(with a continuous clock a SYNC output will always be produced).
Each of the methods will be described in the following sections
and are illustrated in Figures 4 through 9. It should be noted
that all timing diagrams assume that the receiving device is
latching data on the rising edge of the external clock. If the
falling edge of DATACLK is used then, in the case of a discon-
tinuous clock, one less clock pulse is required than shown in
Figures 4 through 7 to latch in a 16-bit word. Note that data is
valid on the falling edge of a clock pulse (for t
13
greater than t
18
)
and the rising edge of the next clock pulse.
The AD974 provides error correction circuitry that can correct
for an improper bit decision made during the first half of the
conversion cycle. Normally the occurrence of an incorrect bit
decision during a conversion cycle is irreversible. This error
occurs as a result of noise during the time of the decision or due
to insufficient settling time. As the AD974 is performing a
conversion it is important that transitions not occur on digital
input/output pins or degradation of the conversion result could
occur. This is particularly important during the second half of
the conversion process. For this reason it is recommended that
when an external clock is being provided it be a discontinuous
clock that is not toggling during the time that BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY low.
EXTERNAL DISCONTINUOUS CLOCK DATA READ
AFTER CONVERSION WITH NO SYNC OUTPUT
GENERATED
Figure 4 illustrates the method by which data from conversion
“n” can be read after the conversion is complete using a discon-
tinuous external clock without the generation of a SYNC
output. After a conversion is complete, indicated by BUSY
returning high, the result of that conversion can be read while
CS is Low and R/C is high. In this mode CS can be tied low.
The MSB will be valid on the first falling edge and the second
rising edge of DATACLK. The LSB will be valid on the 16th
falling edge and the 17th rising edge of DATACLK. A mini-
mum of 16 clock pulses are required for DATACLK if the
receiving device will be latching data on the falling edge of
DATACLK. A minimum of 17 clock pulses are required for
DATACLK if the receiving device will be latching data on the
rising edge of DATACLK.
The advantage of this method of reading data is that data is not
being clocked out during a conversion and therefore conversion
performance is not degraded.
When reading data after the conversion is complete, with the
highest frequency permitted for DATACLK (15.15 MHz), the
maximum possible throughput is approximately 195 kHz, and
not the rated 200 kHz.
EXT
DATACLK
R/C
BUSY
SYNC
DATA
t
12
0 123 141516
t
13
t
14
t
1
t
2
t
21
t
18
t
18
BIT 15
(MSB)
BIT 14 BIT 13 BIT 1
BIT 0
(LSB)
Figure 4. Conversion and Read Timing Using an External Discontinuous Data Clock
(EXT/
INT
Set to Logic High,
CS
Set to Logic Low)
