826646-7 Datasheet BD6762FV-E2, BD6761FS-E2, 826937-6 | P16-P18

BD6761FS,BD6762FV

Technical Note

16/22

www.rohm.com

2010.06 - Rev.

7) Output simultaneous on prevention circuit (BD6761FS, BD6762FV)

When the low-side gate voltage becomes high while the high-side gate voltage is low, or when the high-side gate

voltage becomes high while the low-side gate voltage is low, the simultaneous on prevention time is provided with t=3.2

s (TYP value). When the input capacity of external FET is C and the gate connection resistor is R, set R to satisfy the

following equation so that the simultaneous on prevention time as mentioned above is not exceeded.

Check that the simultaneous on is not made in the actual operation and then set C and R.

Fig.13 High/Low-side Simultaneous On Prevention Timing Chart

8) Short brake (BD6761FS and BD6762FV)

BD6761FS operates the short brake action with the ACC and DEC pins set to low, and BD6762FV does with the SB pin set to

OPEN or high. At the time of short brake, the high-side gate is turned off and the low-side is turned on. At the time of short

brake operating, the current flows to the output FET, which is decided by the motor's counter electromotive voltage and coil

impedance. Since this current flows via path which does not run through the overcurrent protection (current limit) detection

resistor, the overcurrent protection does not operate as IC operating. Therefore, the current more than the overcurrent

protection set current may flow to the output FET, pay attention so that it does not exceed the output FET rating.

9) Forward/reverse rotation circuit (BD6761FS and BD6762FV)

Forward /reverse rotation of motor can be switched according to the FR pin input conditions. Logics of the hall input and

output conditions according to the FR pin input conditions are shown in the I/O conditions table (P.10). If the FR pin is

switched during the motor rotation, since the simultaneous on prevention circuit in IC operates, the feed through current

does not flow. However, since the motor current flows in the direction to the power source due to the electromotive force,

the voltage may be raised if the power source does not have the power supply voltage absorption ability. Examine the

capacitor characteristics between the power supply and ground sufficiently and then pay attention so that the power

supply voltage and step-up voltage do not exceed the absolute maximum ratings. When the physical measures are

taken such as increasing the capacitor value which is connected between the power supply and ground, check the

characteristics enough prior to use.

10) Start/stop circuit (BD6762FV)

When the ST/SP pin is in the sate of OPEN or high, IC becomes standby. In the case of standby, some circuits operation

are turned off to reduce the current consumption.

When the ST/SP pin is in the state of low, IC becomes operating.

11) Low voltage protection circuit (BD6761FS and BD6762FV)

This IC builds in the low voltage protection circuit. When VCC becomes lower than 11.5 V (Typ.), the high-side and

low-side gates are both turned off to make the coil turn off. Protection off voltage is 12.0 V (Typ.) and hysteresis width is

0.5 V (Typ.).Since the motor locking protection detection circuit operates in BD6762FV during the low voltage protection

operation, if the low voltage protection operating time becomes longer than the motor locking protection detection time,

the operation moves to the motor locking protection operation after the low voltage protection operation.

12) Built-in 120° slope PWM logic (BD6762FV)

It is possible to perform 120° drive by setting 120/SL pin to OPEN or making high. 120° slope drive is possible by setting

the 120/SL pin to OPEN or making high. Low noise design is realized by reducing the electromagnetic sound generated

at the time of phase switching by means of gradually changing the output PWM on-duty during 120° slope energization.

However, at the time of startup or the hall input frequency is lower than about 3 Hz (Typ. value), it becomes 120° drive.

When the hall input frequency is more than about 3 Hz (Typ. value) and the rise of hall U-phase is detected 7 times, it

switches to the 120° slope drive.

High-side gate

Low-side gate

t t t t t t

10 ×( 24 + R )

1.8µ

≦

BD6761FS,BD6762FV

Technical Note

17/22

www.rohm.com

2010.06 - Rev.

13) Servo circuit (BD6762FV)

・Frequency multiplication circuit (Dividing period) (BD6762FV)

This IC builds in the frequency multiplication circuit.

Servo circuit is composed of the feedback loop as shown in the diagram and flows in/out the current (22μA: Typ.) to

the LPF pin (30 pin) by detecting the phase difference between the CLKIN pin (29 pin) and the frequency dividing unit

output FCOMP. The phase difference signal output to the LPF pin (30 pin) is smoothed by the filter which is connected

at the IC external of the LPF pin (30 pin) and this voltage is input to the VCO (Voltage control oscillation circuit) to

decide the frequency for the internal signal FVCO. Since the dividing ratio of this frequency dividing unit is set to 1024,

the relation of

FVCO[Hz]=1024・FCOMP[Hz]

can be obtained, and the FCOMP and CLKIN have the same frequency according to the feedback loop as shown in

the following diagram, therefore the multiplied frequency of 1024 times of FCOMP or CLKIN is acquired as the FVCO

frequency.

・Speed discriminator (BD6762FV)

The FGSOUT signal (28 pin) which detects the motor rotation speed and the reference clock in IC are compared and

the acceleration/deceleration signal is output to the DOUT pin (32 pin). Reference clock is the signal (FVCO) that the

CLKIN signal (29 pin) is multiplied by 1024. When the FG period is short to the reference clock period, it is determined

that the motor revolution speed is too fast and the difference from the reference clock period is output to the DOUT pin

as the deceleration command. When the FG period is long, the difference is output as an accelerating command.

・PLL (BD6762FV)

Phases of the FGSOUT (28 pin) signal which detected the motor revolution speed and the CLKIN (29 pin) input from

the external are compared, and if the FG phase leads to CLKIN (28 pin), the difference is output as the deceleration

command. If the FG phase lags, the difference is output as the acceleration command.

・Integration amplifier (BD6762FV)

Speed error of the reference clock which is obtained in the speed discriminator block and the FG signal, and the

phase difference signal of the CLKIN acquired in PLL block and the FG are integrated together and smoothed to

become the DC voltage. This smoothed signal determines the PWM on-duty.

14) Speed lock detection circuit (BD6762FV)

When the motor speed is within 6.25% range to the CLKIN signal (29 pin), L is output to the LD pin (36 pin) output.

Since the LD pin (36 pin) has the open/drain output format, use as it is pulled up to the power supply with the resistor

(100kΩ). At this time, pay attention so that the voltage more than 36 V is not applied to the LD pin.

15) Motor locking protection (BD6762FV)

Motor locking protection circuit judges he motor is in the locking condition when the motor speed is not in the lock range

(preset value: 6.25%) and the motor locking detection time T

elapsed, the high-side and low-side output gates are

both turned off.Motor locking protection can be cleared by making the condition Low after setting the ST/SP pin or the

SB pin to OPEN or making high. Motor locking detection time T

is determined by the capacitor C7 which is connected

to the LP pin and the count number CLP (preset value: 96) of the internal counter.

=2×10

×C7×CLP [S]

ase compara

VCO (Voltage control

oscillation circuit

)

Frequency dividing

unit

(

1024 dividin

CLKIN

FCOMP

FVCO

LPF

BD6761FS,BD6762FV

Technical Note

18/22

www.rohm.com

2010.06 - Rev.

●Selecting application components

Design method Design example

①Output FET

This IC is the predriver for high-side and low-side N-channel

MOS FET drive. Select the FET with the required current

capacity to drive the motor.

Recommended FET RDS035L03 (A)

②Diodes (BD67861FS)

Diodes are required to protect between the gate and source of

output FET.

Recommended diode 1SS355

Insert the diode in the direction from high-side

FET source to the gate side (in the forward direction).

③Protection capacitor between the output FET drain and source

Check the operation so that the voltage between the output FET

drain and source does not exceed the absolute maximum

ratings due to the fluctuation of VCC at the time of PWM driving

and then set the value.

A value of 0.01μ to 0.1μF is recommended.

A value of 0.1μF is appropriate for the capacitance.

Insert the capacitor between the output FET drain and

source. (Position at the close point to FET as much as

possible.)

④VB current capacitance capacitor

Current capacity from VG changes according to the capacitance

to be connected. However, if the capacitance is too large, the

following action is delayed when VCC starts up, and the

magnitude relation becomes VCC > VG which should be VCC <

VG usually and the large current may flow in internal block

circuits and result in damaging the circuits. When VG is directly

supplied from the external block without using the internal

circuits, disconnect the capacitor between CP1 and CP2, and

connect the 20kΩ resistor (for noise reduction) between CP1

and ground to use.

A value of 0.01μF is appropriate for the capacitor

between CP1 and CP2

(A value of 0.01μF 0.1μF is recommended.)

A value of 0.1μF is appropriate for the capacitor

between VG and VCC.

⑤PWM frequency

PWM frequency can be adjusted by the capacitance and

resistance to connect. When the frequency is high, the heat

generation increases due to switching loss. When the frequency

is low, it enters audible range. Check the operation with the

actual product and determine the constant.

The following constants are appropriate.

BD6761FS Cfe=1000pF, Rfe=50kΩ, fo=16.5kHz(TYP.)

BD6762FV Cfe=1000pF, Rfe=20kΩ, fo=16.0kHz(TYP.)

⑥Hall input level

The current value to feed to the hall element changes by

changing the resistance and the amplitude level of hall element

can be adjusted.

Amplitude level increases when the resistance value is chosen

smaller by considering the noise affect, but pay attention also to

the hall input voltage range. BD6761FS (1.5V to 4.1V) and

BD6762FV (0V to 3V)

Connect to the transistor base via 1k resistor (base

current limit) from the VREG pin. Connect the transistor

collector to VCC, the emitter to the hall element via R1.

Connect the ground side of hall element to the ground

via R2.

A value of 200Ω to 1kΩ is recommended. A value of

200Ω is appropriate, respectively. When connecting to

the VCC side directly with R1, values of R1=5kΩ and

R2=2kΩ are appropriate.

⑦VREG

VREG which is the internal voltage output pin drives the circuits

in IC. Connect the capacitor to stabilize it.

A value of 0.01μF to 0.1μF is recommended. A value of

0.1μ is appropriate.

⑧Current limit

The current flowing to FET can be controlled by setting the

resistance value. Determine the constant according to the motor

specifications.

Following equation shows the current value.

BD6761FS Iomax=0.48/RNF [A]

BD6762FV Iomax=0.26/RNF [A]

⑨Hall input noise

Insert capacitors between the hall phases in order to eliminate

the hall input noise due to the effect by the pattern routing

design.

A value of 0.01μF is appropriate for the capacitor to be

installed between the hall phases.

A value of 0.01μF to 0.1μF is recommended.

⑩CL (RF) voltage smoothing low pass filter

Smooth the CL (RF) voltage which has PWM noise through the

low pass filter.

A value of C = 470pF and R=1k is appropriate for the

low pass filter.

For the external constant, since the impedance is high,

make sure to design the pattern with the shortest circuit

route so that the circuit is hard to be affected by noise.

⑪FG AMP constant setting

FG AMP gain: GFG is the ratio of R1 and R2 calculated by the

following equation.

GFG=20log R2/R1 [dB]

Set up the gain so that the FGOUT amplitude is large enough to

the hysteresis level of the hysteresis comparator and it cannot

be clamped by the high and low output voltages

(VFGOH and VFGOL).

R1 and C1 form a high pass filter and R2 and C2 form a

low pass filter. Each cut off frequency; fMPF and fLPF

is determined by the following equation.

fMPF=1/2πR1C1, fLPF=1/2πR2C2

Set the value so that the main signal from PG by the

motor is not attenuated but the unnecessary noise can

be attenuated.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

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