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826646-7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
BD6761FS,BD6762FV
Technical Note
19/22
www.rohm.com
2010.06 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
Design method Design example
⑫Phase compensation capacitor (BD6761FS)
Phase compensation is performed in the output of the CS
amplifier. The capacitance value should be selected according
to the servo constant, and proper motor operation should be
confirmed. When the capacitance is large, the I/O response
becomes bad. When it is small, the output becomes easy to
oscillate.
A value of 0.001μF to 0.1μF is recommended.
A value of 0.001μF is appropriate for BA6680FS.
A value of 0.1μF is appropriate for BD6761FS.
⑬VCC pin
Set up the capacitance for the stabilization and noise reduction
on the power line.
A value of value 1μF to 10μF is recommended.
A value of 10μF is appropriate.
⑭Charge pump filter(BD6761FS)
Filter composed of C3, C4 and R3 smoothes the current pulses
output from the CPOUT pin and converts it to DC.
This impedance Z is shown by the following equation.
When the pole frequency is set to fP1 and fP2, they are:
fP1=ω
1
/2π=1/2π(C3//C4)R3
fP2=ω
2
/2π=1/2πC4R3
Recommended value
C3: 0.01μF to 0.1μF; a value of 0.01μF is appropriate.
C4: 0.033μF to 0.33μF; a value of 0.1μF is appropriate.
R3 : 30kΩ to 300kΩ; a value of 100kΩ is appropriate.
⑮Output FET gate voltage stabilization resistor
When the noise is generated at the time of external MOSFET
on/off due to the rise and fall speed of the IC output, insert the
resistor between the IC output and external MOSFET gate.
Establish R so that the simultaneous on prevention time
is not exceeded as shown in 7). Output simultaneous on
prevention circuit in P.17/24 Operating Explanation.
A value of R = 0Ω is appropriate.
⑯Peak hold setting capacitor (BD6761FS)
Charges the peak hold on the voltage at the current detection
pin CL.
A value of 0.33μF is appropriate.
⑰Motor locking detection time setting capacitor (BD6762FV)
Motor locking detection time T
LP
is determined by the capacitor
C7 which is connected to the LP pin and the count number CLP
(Preset value: 96) of the internal counter. The T
LP
is shown by
the following equation.
TLP=2×10
5
×C7×96
A value of 0.22μF is appropriate.
⑱Integration amplifier constant setting (BD6762FV)
Speed discriminator side current value ID is shown by|I
D
|=2.5/R4
and the PLL side current value IP is shown by|I
P
|=2.5/R5.
Therefore, the current I
IN
which flows in the integration AMP
input pin INTIN is shown by I
IN
=I
D
+I
P.
The larger the I
IN
is, the higher the integration amplifier gain
becomes.
Gains of the speed discriminator and PLL can be set by
adjusting R4 and R5.
Gain G is shown by the following equation.
When the pole frequency is set to fP1 and fP2, they are:
fP1=ω
1
/2π=1/2π(C5//C6)×R6
fP2=ω
2
/2π=1/2πC6R6
Recommended value
R4: 10kΩ to 40kΩ; a value of 20 kΩ is appropriate.
R5: 300kΩ to 3MΩ; a value of 1 MΩ is appropriate.
R6: 100kΩ to 500kΩ; a value of 220 kΩ is appropriate.
C5: 0.01μF to 0.1μF; a value of 0.047μF is appropriate.
C6: 0.033μF to 1.0μF; a value of 0.47μF is appropriate.
⑲LPF external constant (BD6762FV)
Filter composed of C8, C9 and R7 smoothes the current pulses
output from the LPF pin and converts it to DC.
This impedance Z is shown by the following equation.
When the pole frequency is set to fP1 and fP2, they are:
fP1=ω
1
/2π=1/2π(C8//C9)R7 fP2=ω
2
/2π=1/2πC9R7
Recommended value
C8: 0.1μF to 0.6μF; a value of 0.33μF is appropriate.
C9: 0.1μF to 0.6μF; a value of 0.33μF is appropriate.
R7: 0.5kΩ to 10kΩ; a value of 2kΩ is appropriate.
※Setting values in these materials are only for reference. Actual set may change its characteristics due to the boards layout, wiring and components type to use.
Please perform the sufficient verification using the actual product for the field operation.
G =
C6
C5+C6
×
S+ω
2
S
ω
1
S 1+
R6
R4 // R5
×
Z = R3×
C
4
C3+C4
×
S+ω
2
S
ω
1
S 1+
Z = R7×
C9
C8+C9
×
S+ω
2
S
ω
1
S 1+
BD6761FS,BD6762FV
Technical Note
20/22
www.rohm.com
2010.06 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
●Notes for use
(1) Absolute maximum ratings
This product is subject to a strict quality management regime during its manufacture. Use of the IC in excess of absolute
maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions
should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical
safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute
maximum ratings may be exceeded is anticipated.
(2) Connecting the power supply connector backward
Connecting the power supply connector backwards may result in damage to the IC. For the protection of the IC from
reversed connections, provide an appropriate measure, such as the insertion of an external diode each between the
power supply and the power supply pin of the IC and between the motor coils.
(3) Power supply lines
The regenerated current resulting from the back EMF of the motor will return. Therefore, take an appropriate measure,
such as the insertion of a capacitor between the power supply and GND. Determine the capacitance in full consideration
of all the characteristics of the electrolytic capacitor, because the electrolytic capacitor may loose some capacitance at
low temperatures. If the connected power supply does not have sufficient current absorption capacity, regenerative
current will cause the voltage on the power supply line to rise, which combined with the product and its peripheral
circuitry may exceed the absolute maximum ratings. It is recommended to implement a physical safety measure such as
the insertion of a voltage clamp diode between the power supply and GND pins.
(4) GND potential
Ensure a minimum GND pin potential in all operating conditions.
(5) Setting of heat
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating
conditions.
(6) Pin shorts and mistake fitting
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result
in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by
the presence of a foreign object may result in damage to the IC.
(7) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction.
(8) ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.
(9) Thermal shutdown circuit (TSD)
This IC incorporates a TSD circuit. If the chip becomes the following temperature, coil output to the motor will be open.
The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the
IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment
where the operation of the TSD circuit is assumed.
TSD on temperature [°C]
(Typ.)
Hysteresis temperature [°C]
(Typ.)
BD6761FS 175 35
BD6762FV 175 23
(10) PWM drive
Voltage between the output FET drain and source may exceed the absolute maximum ratings due to the fluctuation of
VCC at the time of PWM driving. If there is the threat of this problem, it is recommended to take physical
countermeasures for safety such as inserting the capacitor between the VCC pin of FET and the detection resistor pin.
(11) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to
stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic
measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before
connecting it to or removing it from a jig or fixture during the inspection process.
BD6761FS,BD6762FV
Technical Note
21/22
www.rohm.com
2010.06 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
(12) Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated.
P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of
parasitic elements.
For example, when a resistor and transistor are connected to pins as shown in Fig. 14,
○ the P/N junction functions as a parasitic diode
when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).
○ Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines
with the N layer of other adjacent elements to operate as a parasitic NPN transistor.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result
of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC
malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will
trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (P substrate)
voltage to input pins.
(13) Ground Circuit Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change
the GND wiring pattern of any external parts, either.
Fig. 14 Mimetic Diagram of Parasitic Element
Resistor Transistor (NPN)
N
N N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin A
N
N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin B
C
B
E
N
GND
Pin A
P
aras
iti
c
element
Pin B
Other adjacent elements
E
B C
GND
P
aras
iti
c
element
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

826646-7

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Manufacturer:
TE Connectivity / AMP Connectors
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Headers & Wire Housings 1X07 POS VERT AU
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