BD6761FS,BD6762FV
Technical Note
4/22
www.rohm.com
2010.06 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
BD6762FV (Unless otherwise specified, Ta=25°C, VCC=24 V)
Parameter Symbol
Limits
Unit Conditions
Min. Typ. Max.
Start/Stop
High-level ST/SP input voltage VSTH 2.2 VREG V STOP
Low-level ST/SP input voltage VSTL 0 0.8 V START
High-level ST/SP input current ISTH -10 0 10 μA
Low-level ST/SP input current ISTL -70 -50 -30 μA
Forward rotation/Reverse rotation
High-level FR input voltage VFRH 2.2 VREG V Reverse rotation
Low-level FR input voltage VFRL 0 0.8 V Forward rotation
High-level FR input current IFRH -10 0 10 μA
Low-level FR input current IFRL -70 -50 -30 μA
120°/Slope switching
High-level 120/slope input voltage VANH 2.2 VREG V 120°
Low-level 120/slope input voltage VANL 0 0.8 V 120° slope
High-level 120/slope input current IANH -10 0 10 μA
Low-level 120/slope input current IANL -70 -50 -30 μA
Short brake
High-level SB input voltage VSBH 2.2 VREG V Short brake operation
Low-level SB input voltage VSBL 0 0.8 V Short brake clear
High-level SB input current ISBH -10 0 10 μA
Low-level SB input current ISBL -70 -50 -30 μA
Current limit
Current detection voltage VCL 0.23 0.26 0.29 V
Booster
CP1 oscillating frequency FCP1 75 125 175 kHz
VG step-up voltage VG VCC+5.7 VCC+6.7 VCC+7.7 V
High-side output
High output voltage 1 VHHG1 VCC+5.8 VCC+6.8 VCC+7.8 V VG=31V
High output voltage 2 VHHG2 VCC+3.8 VCC+4.8 VCC+5.8 V Io=-1mA
Low output voltage 1 VHLG1 0.1 0.3 V
Low output voltage 2 VHLG2 0.5 1.0 V Io=5mA
Clamp voltage VHCL 10 11 12 V
Low-side output
High output voltage 1 VLHG1 9.8 10.8 11.8 V
High output voltage 2 VLHG2 9.0 10.0 11.0 V Io=-5mA
Low output voltage 1 VLLG1 0.1 0.3 V
Low output voltage 2 VLLG2 0.3 0.5 V Io=5mA
BD6761FS,BD6762FV
Technical Note
5/22
www.rohm.com
2010.06 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
Reference Data
Power Dissipation Reduction
0
200
400
600
800
1000
1200
0 25 50 75 100 125 150
Ambient Temperature: Ta(
)
Power Dissipation : Pd
mW)
950
0
200
400
600
800
1000
1200
0 25 50 75 100 125 150
Ambient Temperature: Ta(
)
Power Dissipation : Pd
mW)
1100
Fig.7 BD6761FS Power Dissipation Reduction
Reduced by 7.6 mW/°C over 25°C, when mounted on a
glass epoxy board (70 mm 70 mm 1.6 mm).
Fig.8 BD6762FV Power Dissipation Reduction
Reduced by 8.8 mW/°C over 25°C, when mounted on a
glass epoxy board (70 mm 70 mm 1.6 mm)/℃で軽減。
0
5
10
15
20
25
16 21 26 31 36
Supply voltage :VCC[V]
ICC[mA]
5.0
5.5
6.0
6.5
7.0
0 2.5 5 7.5 10
VREG current : IVREG[mA]
VREG[V]
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
012345
VG current : IVG[mA]
VG[V]
0
5
10
15
20
25
16 21 26 31 36
Supply voltage :VCC[V]
ICC[mA]
4.0
4.5
5.0
5.5
6.0
0 2.5 5 7.5 10
VREG current : IVREG[mA]
VREG[V]
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
012345
VG current : IVG[mA]
VG[V]
25
-35
75
Fig.1 Circuit current (BD6761FS) Fig. 2 VREG Voltage (BD6761FS)
25
-35
75
Fig. 3 VG Voltage (BD6761FS)
75
25
-35
25
-25
75
Fig.4 Circuit current (BD6762FV) Fig.5 VREG Voltage (BD6762FV)
25
-25
75
Fig.6 VG Voltage (BD6762FV)
75
25
-25
BD6761FS,BD6762FV
Technical Note
6/22
www.rohm.com
2010.06 - Rev.
A
© 2010 ROHM Co., Ltd. All rights reserved.
Block Diagram, Application Circuit Diagram, and Pin Function
1)BD6761FS
Fig.9 BD6761FS Block Diagram
BD6761FS pin Function
No.
Pin
name
Function No.
Pin
name
Function
1 GND GND pin 17 RFE CFE current control pin
2 CP1 CP1 pin 18 CFE PWM frequency control pin
3 UHG U-phase high-side FET gate pin 19 CNF Phase compensation pin
4 ULG U-phase low-side FET gate pin 20 F/R Forward/reverse rotation switching pin
5 VHG V-phase high-side FET gate pin 21 DEC Deceleration signal input pin
6 VLG V-phase low-side FET gate pin 22 ACC Acceleration signal input pin
7 WHG W-phase high-side FET gate pin 23 RCP CPOUT current control pin
8 WLG W-phase low-side FET gate pin
24 CPOUT
Charge pump output /
Torque control signal input pin
9 CL Motor current detection pin
10 PH Peak hold pin 25 VREG VREG pin
11 HU+
Hall signal input pin
26 FGIN+ FG input + pin
12 HU-
Hall signal input pin
27 FGIN- FG input - pin
13 HV+
Hall signal input pin
28 FGOUT FG output pin
14 HV-
Hall signal input pin
29 FGSOUT FGS output pin
15 HW+
Hall signal input pin
30 VCC VCC pin
16 HW-
Hall signal input pin
31 VG Boost pin
32 CP2 CP2 pin
RNF
R2
FGIN-
CPOUT
ACC
DEC
F/R
GND
CP1
UHG
ULG
VHG
VLG
WHG
WLG
CL
PH
Hall AMP
BOOSTER
CHARGE
PUMP
PRE DRIVE
MOS
FET
MOS
FET
MOS
FET
HU+
HU-
HV+
HV-
HW+
HW-
VG
VCC
FGOUT
RCP
CNF
CFE
RFE
FGSOUT
FGIN+
VREG
TRAIANGLE
WAVE
GENERATOR
CP2
LOGIC
PEAK
HOLD
SHORT
BRAKE
SLEW
RATE
DETECT
HW
HV
HU
TSD
REGURATOR
10.5V
REGURATOR
10.5V
UVLO
EDGE
DETECT
CURRENT
LIMIT
S
R
Q
Q
CURRENT
SENSE AMP
VCL1
TORQUE
AMP
OUTPUTOFF
COMP
VCL2
1pin 32pin
16pin 17pin
M
0.12
1k
200
(200
~ 1k)
50k
(50k ~ 100k)
R3
100k
R1 200(200 ~ 1k)
1k
R1
820
10k
(1k ~ 100k)
R2
82k
0.1µF
0.1µF
0.1µF
470pF
0.033µF
(0.01µF ~ 0.1µF)
0.01µF
0.01µF
0.01µF
1000pF (500pF ~ 2000pF)
0.1µF
0.33µF
0.1µF
(0.01µF~0.1µF)
0.022µ
0.22µF
C1
0.47µF
C2
1500pF
10µF
0.1µF
0.01µF
(0.01µF ~ 0.1µF)
470pF
470pF
Capacitor, diode for the
protection between the
output FET drain and
source
See P. 18/22.
Resistor for setting
the current limit
See P. 18/22.
CL voltage smoothing
low pass filter
See P. 18/22.
Capacitor for Hall
noise elimination
See P. 18/22.
100k
Capacitor for setting
VG current capacity
See P. 18/22.
Resistor for setting FG
amplifier gain and the
capacitor for the filter
See P. 18/22.
For setting Hall
input level
See P. 18/22.
Capacitor for preventing
VREG oscillation
See P. 18/22.
Capacitor for setting the
phase compensation
See P. 19/22.
External constant for
setting PWM frequency
See P. 18/22.
MOS FET
Capacitor for setting
the peak hold
See P. 19/22.
Capacitor, resistor for
setting the charge pump
See P. 19/22.
FGSOUT pull-up
resistor
See P. 20/22.
Output FET gate
voltage stabilization
resistor
See P.19/22.
C4
C3
Capacitor for VCC pin
noise elimination
See P. 19/22.

826646-7

Mfr. #:
Manufacturer:
TE Connectivity / AMP Connectors
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Headers & Wire Housings 1X07 POS VERT AU
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