IDT
®
Programmable Timing Control Hub
TM
for Mobile P4
TM
Systems 0930A—04/13/10
954226
Programmable Timing Control Hub
TM
for Mobile P4
TM
Systems
4
MLF Pin Description
PIN # PIN NAME TYPE DESCRIPTION
1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
2 ITP_EN/PCICLK_F0 I/O
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
3 **SELPCIEX_LCDCLK#/PCICLK_F1 I/O
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX /
Free running 3.3V PCI clock output.
4 Vtt_PwrGd#/PD IN
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
cry stal oscillator are stopped.
5 VDD48 PWR Power pin for the 48MHz output.3.3V
6 FSLA/USB_48MHz I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
7 GND PWR Ground pin.
8 DOTT_96MHz OUT
Free running PCI clock not affected by PCI_STOP# through I2C .
ITP_EN: latched input to select pin functionality
1 = CPU_2_ITP pair
0 = PCIEX_6 pair
9 DOTC_96MHz OUT Complement clock of differential pair for 96.00MHz DOT clock.
10 FSLB/TEST_MODE IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
11 LCDCLK_SS/PCIEXT0 OUT
True clock of LCDCLK_SS output / True clock of PCI Express differential
pair. Selected by SELPCIEX_LCDCLK#
12 LCDCLK_SS/PCIEXC0 OUT
Complementary clock of LCDCLK_SS output / Complementary clock of PCI
Express differential pair. Selected by SELPCIEX_LCDCLK#
13 PCIEXT1 OUT True clock of differential PCI_Express pair.
14 PCIEXC1 OUT Complement clock of differential PCI_Express pair.
15 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V
16 PCIEXT2 OUT True clock of differential PCI_Express pair.
17 PCIEXC2 OUT Complement clock of differential PCI_Express pair.
18 PCIEXT3 OUT True clock of differential PCI_Express pair.
19 PCIEXC3 OUT Complement clock of differential PCI_Express pair.
20 SATACLKT OUT True clock of differential SATA pair.
21 SATACLKC OUT Complement clock of differential SATA pair.
22 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V
23 GND PWR Ground pin.
24 PCIEXC4 OUT Complement clock of differential PCI_Express pair.
25 PCIEXT4 OUT True clock of differential PCI_Express pair.
26 PEREQ2#*/PCIEXC5 I/O
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of
differential PCI Express output.
27 PEREQ1#*/PCIEXT5 I/O
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / True clock of
differential PCI Express output.
28 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V
