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954226AGLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
IDT
®
Programmable Timing Control Hub
TM
for Mobile P4
TM
Systems 0930A—04/13/10
954226
Programmable Timing Control Hub
TM
for Mobile P4
TM
Systems
7
Table2: LCDCLK Spread and Frequency Selection Table
Pin
17/18
MHz
0 0 0 0 0 96.00
0 0 0 0 1 96.00
0 0 0 1 0 96.00
0 0 0 1 1 96.00
0 0 1 0 0 96.00
0 0 1 0 1 96.00
0 0 1 1 0 96.00
0 0 1 1 1 96.00
0 1 0 0 0 96.00
0 1 0 0 1 96.00
0 1 0 1 0 96.00
0 1 0 1 1 96.00
0 1 1 0 0 96.00
0 1 1 0 1 96.00
0 1 1 1 0 96.00
0 1 1 1 1 96.00
10000100.00
10001100.00
10010100.00
10011100.00
10100100.00
10101100.00
10110100.00
10111100.00
11000100.00
11001100.00
11010100.00
11011100.00
11100100.00
11101100.00
11110100.00
11111
100.00
Byte 6b7 Byte 6b6 Byte 6b5 Byte 6b4 Byte 6b3
Spread
%
0.8 Down
1 Down
1.25 Down
1.75 Down
1.5 Down
2.5 Down
2 Down
3 Down
+/-0.3 Center
+/-0.4 Center
+/-0.5 Center
+/-0.6 Center
+/-0.8 Center
+/-1.0 Center
+/-1.25 Center
+/-1.5 Center
0.8 Down
1 Down
1.25 Down
1.5 Down
1.75 Down
2 Down
2.5 Down
3 Down
+/-0.3 Center
+/-1.0 Center
+/-1.25 Cente
r
+/-1.5 Center
+/-0.4 Center
+/-0.5 Center
+/-0.6 Center
+/-0.8 Center
IDT
®
Programmable Timing Control Hub
TM
for Mobile P4
TM
Systems 0930A—04/13/10
954226
Programmable Timing Control Hub
TM
for Mobile P4
TM
Systems
8
General SMBus serial interface information for the 954226
* By default, SMBADR = 0,
therefore, SMBus WRITE/READ address is D0/D1.
Please see SMBus Address Selection table on page 1.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
IDT
®
Programmable Timing Control Hub
TM
for Mobile P4
TM
Systems 0930A—04/13/10
954226
Programmable Timing Control Hub
TM
for Mobile P4
TM
Systems
9
SMBus Table: Output Control Register
Control
Function
Bit 7
CPUCLK2_ITP/PCIEX6
Enable
Output Enable RW 1
Bit 6
PCIEX5 Enable Output Enable RW 1
Bit 5
PCIEX4 Enable Output Enable RW 1
Bit 4
SATACLK Enable Output Enable RW 1
Bit 3
PCIEX3 Enable Output Enable RW 1
Bit 2
PCIEX2 Enable Output Enable RW 1
Bit 1
PCIEX1 Enable Output Enable RW 1
Bit 0
LCDCLK/PCIEX0 Enable Output Enable RW 1
SMBus Table: Spread and Output Control Register
Control
Function
Bit 7
Test Clock Mode Entry Test Mode RW 0
Bit 6
DOT_96MHz Enable Output Enable RW 1
Bit 5
USB_48MHz Enable Output Enable RW 1
Bit 4
REF_0 Enable Output Enable RW 1
Bit 3
LCDCLK/PCIEX0 Spectrum
Mode
Spread Control RW 1
Bit 2
CPUCLK1 Output Enable RW 1
Bit 1
CPUCLK0 Output Enable RW 1
Bit 0
Spread Spectrum Mode Spread Control for PLL1 RW 0
SMBus Table: Output Control Register
Control
Function
Bit 7
PCICLK5 Output Enable RW 1
Bit 6
PCICLK4 Output Enable RW 1
Bit 5
PCICLK3 Output Enable RW 1
Bit 4
PCICLK2 Output Enable RW 1
Bit 3
Test Mode Selection Test Mode Selection RW 0
Bit 2
PCI_STOP
Stop all PCI, PCIEX and
SATA clocks
RW 1
Bit 1
PCI_F0 Enable Output Enable RW 1
Bit 0
PCI_F1 Enable Output Enable RW 1
SMBus Table: Output Control Register
Control
Function
Bit 7
PCIEX6 RW 0
Bit 6
PCIEX5 RW 0
Bit 5
PCIEX4 RW 0
Bit 4
SATACLK RW 0
Bit 3
PCIEX3 RW 0
Bit 2
PCIEX2 RW 0
Bit 1
PCIEX1 RW 0
Bit 0
PCIEX0 RW 0
Disable Enable
Disable Enable
Disable Enable
OFF ON
-
Disable Enable
Disable Enable
Enable
Disable Enable
Disable
-
-
Enable
Disable Enable
-
-
-
-
- Disable Enable
Enable
Enable
OFF
Disable
Disable
ON
PWD01Byte 1 Pin # Name Type
-
-
-
-
-
-
Disable Enable
01
Disable Enable
PWD
-
Byte 0 Pin # Name Type
- Disable
-
Free Running
-
Allow assertion of
PCI_STOP# or s etting of
PCI_STOP control bit in
SMBus register to stop
PCIEX clocks
Free Running
Free Running Stoppable
Stoppable
Free Running
Stoppable
-
-
Enable
Stoppable
Disable
Disable
-
-
Enable
PWD
PWD
Stoppable
Enable
1
Enable
Stoppable
Disable
Stoppable
Enable
0
Disable
Byte 2 Pin # Name Type
-
0
Disable
Byte 3
Hi-Z
Pin # Name Type
Disable
-
-
-
-
-
-
-
-
-
Disable
Free Running Stoppable
Free Running
Enable
1
REF/N
Free Running
Free Running
Enable
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

954226AGLF

Mfr. #:
Buy 954226AGLF
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner PC AMIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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