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IRS20955STRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
IRS20955(S)PbF
www.irf.com 13
OC
REF
OCREF
COM
OCSET
VS
OC
+
-
IRS20955
OC Comparator
R4
R5
-B
+B
OUT
Q1
Q2
LO
LO
0.5mA
5.1V
Figure 13. Low-Side Over-Current Sensing
Low-Side Over-Current Setting
Let the low-side MOSFET have an R
DS(ON)
of 100
mΩ and set the current trip level to 30 A. V
OCSET
is
given by:
V
OCSET
= I
TRIP+
x R
DS(ON)
= 30 A x 100 mΩ = 3.0 V
Choose R4+R5=10 kΩ to properly load the VREF
pin.
Ω=
Ω⋅=
Ω⋅=
k
k
V
V
k
V
V
R
REF
OCSET
8.5
10
1.5
0.3
10
5
where V
REF
= 5.1 V
Based on the E-12 series of resistor values, choose
R5 to be 5.6 kΩ and R4 to be 3.9 kΩ to complete
the design.
In general, R
DS(ON)
has a positive temperature
coefficient that needs to be considered when setting
the threshold level. Variations in R
DS(ON)
will affect
the selection of external or internal component
values.
High-Side Over-Current Sensing
For positive load currents, high-side over-current
sensing also monitors the load condition and shuts
down the switching operation if the load current
exceeds the preset trip level.
High-side current sensing is based on the
measurement of V
DS
across the high-side MOFET
during high-side turn on through pins CSH and VS.
In order to avoid triggering OCP from overshoot, a
blanking interval inserted after HO turn on disables
over-current detection for 450 ns.
In contrast to low-side current sensing, the threshold
at which the CSH pin engages OC protection is
internally fixed at 1.2 V. An external resistive divider
R2 and R3 can be used to program a higher
threshold.
An external reverse blocking diode, D1, is required
to block high voltages from feeding into the CSH pin
while the high-side is off. Due to a forward voltage
drop of 0.6 V across D1, the minimum threshold
required for high-side over-current protection is 0.6
V.
()
)1()(
32
3
DFHIGHSIDEDSCSH
VV
R
R
R
V +⋅
+
=
where V
DS(HIGH SIDE)
= the drain to source voltage of
the high-side MOSFET during high-side turn on
V
F(D1)
= the forward drop voltage of D1
Since V
DS(HIGH SIDE)
is determined by the product of
drain current I
D
and R
DS(ON)
of the high-side
MOSFET. V
CSH
can be rewritten as:
()
)1()(
32
3
DFDONDSCSH
VIR
R
R
R
V +⋅⋅
+
=
Note: The reverse blocking diode D1 is forward
biased by a 10 kΩ resistor R1 when the high-side
MOSFET is on.
IRS20955(S)PbF
www.irf.com 14
VS
OC
+
-
IRS20955
CSH
Comparator
-B
+B
OUT
Q1
Q2
HO
LO
HO
R1
R2
R3
D1
VB
CSH
Vcc
1.2V
Figure 14. Programming High-Side Over-Current Threshold
High-Side Over-Current Setting
Figure 14 demonstrates the typical circuitry used for
high-side current sensing. In the following example,
the over-current protection level is set to trip at 30 A
using a MOSFET with an R
DS(ON)
of 100 mΩ. The
component values of R2 and R3 can be calculated
using the following formula:
Let R2 + R3=10 kΩ.
FDS
OCH
VV
Vth
kR
+
⋅Ω= 10
3
where V
th,OCL
= 1.2 V
V
F
= the forward voltage of reverse blocking
diode D1 = 0.6 V.
V
DS@ID=30A
= the voltage drop across the
high-side MOSFET when the MOSFET current is 30
A.
Therefore, V
DS@ID=30A
= I
D
x R
DS(ON)
= 30 A x 100 mΩ
= 3 V
Based on the formulas above, R2 = 6.8 kΩ and R3
= 3.3 kΩ.
Choosing the Right Reverse Blocking Diode
The selection of the appropriate reverse blocking
diode used in place of D1 depends on its voltage
rating and speed. To effectively block bus voltages,
the reverse voltage must be higher than the voltage
difference between +B and -B and the reverse
recovery time must be as fast as the boot strap
charging diode. A diode such as the Philips BAV21
W, a 200 V, 50 ns high speed switching diode, is
more than sufficient.
Deadtime Generator
Deadtime is a blanking period inserted between
high-side turn on and low-side turn on to prevent
shoot through. In the IRS20955S, an internal dead-
time generation block allows the user to select the
optimum deadtime from a range of preset values.
Selecting a preset deadtime through the DT/SD pin
voltage can easily be done through an external
voltage divider. This way of setting deadtime
prevents outside noise from modulating the
switching timing, which is critical to the audio
performances.
How to Determine Optimal Deadtime
The effective deadtime in an actual application
differs from the deadtime specified in this datasheet
due to the switching fall time,
t
f
.. The deadtime value
in this datasheet is defined as the time period
between the beginning of turn-off on one side of the
switching stage and the beginning of turn-on on the
other side as shown in Figure 15. The fall time of
MOSFET gate voltage must be subtracted from the
deadtime value in the datasheet to determine the
effective deadtime of a Class D audio amplifier.
(Effective deadtime) = (Deadtime in datasheet) –
t
f
.
IRS20955(S)PbF
www.irf.com 15
HO (or LO)
LO (or HO)
tf
Dead-time
in
datasheet
Effective dead -time
10%
10%
90%
Figure 15. Effective Deadtime
A longer deadtime period is required for a MOSFET
with a larger gate charge value because of the
longer
t
f
.. Although a shorter effective deadtime
setting is beneficial to achieving better linearity in
Class D amplifiers, the likelihood of shoot-through
current increases with narrower deadtime settings.
Negative values of effective deadtime may cause
excessive heat dissipation in the MOSFETs, leading
to potentially serious damage.
To calculate the optimal deadtime in a given
application, the fall time t
f
for both HO and LO in the
actual circuit need to be taken into account. In
addition, variations in temperature and device
parameters could also affect the effective deadtime
in the actual circuit. Therefore, a minimum effective
deadtime of 10 ns is recommended to avoid shoot-
through current over the range of operating
temperatures and supply voltages.
Programming Deadtime
The IRS20955S selects the deadtime from a range
of preset deadtime values based on the voltage
applied at the DT pin. An internal comparator
translates the DT input to a predetermined dead-
time by comparing the input with internal reference
voltages. These internal reference voltages are set
in the IC through a resistive voltage divider using
V
CC.
The relationship between the operation mode
and the voltage at DT pin is illustrated in the
Figure16 below.
Vcc 0.57xVcc 0.36 xVcc 0.23xVcc
45nS
35nS
25nS
15nS
V
DT
Dead- time
Figure 16. Deadtime vs. V
DT
Table 1 suggests pairs of resistor values used in the
voltage divider for selecting deadtime. Resistors
with up to 5% tolerance are acceptable when using
these values.
Vcc
COM
DT
>0.5mA
R1
R2
IRS20955
Figure 17. External Voltage Divider
Table 1 Recommended Resistor Values for Deadtime Selection
Deadtime Mode R1 R2 DT/SD Voltage
DT1
<10 kΩ
Open V
CC
DT2
5.6 kΩ 4.7 kΩ
0.46(V
CC
)
DT3
8.2 kΩ 3.3 kΩ
0.29(V
CC
)
DT4 Open
<10 kΩ
COM
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IRS20955STRPBF

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Description:
Gate Drivers SOIC
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