IRS20955(S)PbF
www.irf.com 9
Functional Description
Floating PWM Input
The IRS20955S accepts floating inputs, enabling
easy half-bridge implementation. V
DD
, CSD and IN
refer to V
SS
. As a result, the PWM input signal can
directly feed into IN while referencing V
SS
, which is
typically the midpoint between the positive and
negative DC bus voltages in a half-bridge
configuration.
The IRS20955S also accepts a non-floating input
when V
SS
is tied to COM.
IN
VDD
VSS
10.2V
HV
LEVEL
SHIFT
CSD
PROTECTION
Floating Input Isolation
COM
Floating Bias
IRS20955
0V – 200V
Figure 5. Floating PWM Input Structure
Over-Current Protection (OCP)
The IRS20955S features over-current protection to
protect the power MOSFETs during abnormal load
conditions. The IRS20955S engages a sequence of
events when it detects the over-current condition
during high-side or low-side turn on.
As soon as either the high-side or low-side current
sensing block detects over-current:
1. The OC Latch (OCL) flips logic states and
shutdowns the outputs LO and HO.
2. The CSD pin starts discharging the external
capacitor C
t
.
3. When V
CSD
, the voltage across C
t
, falls
below the lower threshold V
th2
, an output
signal from COMP2 resets OCL.
4. The CSD pin starts charging the external
capacitor C
t
.
5. When V
CSD
goes above the upper threshold
V
th1
, the logic on COMP1 flips and the IC
resumes operation.
As long as the over-current condition exists, the IC
will repeat the over-current protection sequence.
Figure 6. Over-Current Protection Timing Chart
